Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2000-12-27
2003-02-18
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S230000, C257S233000, C257S432000, C257S435000
Reexamination Certificate
active
06521920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to solid state image sensors such as CCD image sensors, CMOS image sensors, and the like.
2. Description of the Related Art
As a solid state image sensor, one type of solid state image sensor in which an excessive potential in a photo sensor area is drained to a substrate, also known as a vertical overflow drain-type solid state image sensor, is known in the art.
The vertical overflow drain-type solid state image sensor has been developed to comprise a photo-sensing area with a deeply formed depletion region so that the sensor will be sensitive even in the near-infrared region.
FIG. 7
is a cross-section showing the structure of pixels of a conventional CCD image sensor
1
, which is sensitive also in the near-infrared region.
In the CCD image sensor
1
, a first semiconductive well region
3
of a second conductivity type, i.e., a p-type, which serves as an overflow barrier region is formed on a semiconductive substrate
2
formed by silicon of a first conductivity type, for example, an n-type. On the first p-type semiconductive well region
3
, a high-resistance region
4
having high specific resistance, such as a p
−
-region, an undoped region, an n
−
-region, or the like, is formed.
On the surface of the high-resistance region
4
, an n
+
-type semiconductive region
6
and a p
+
positive charge storage region
7
on the n
+
-type semiconductive region
6
are formed so as to constitute a photo-sensing area
5
, a plurality of which are arrayed in a matrix. The p
+
positive charge storage region
7
inhibits dark current due to the energy level at the interface. The n
+
-type semiconductive region
6
functions as a charge storage region. In the high-resistance region
4
beneath the n
+
-type semiconductive region
6
, an n
−
-type semiconductive region
20
having a higher dopant concentration than that in the high-resistance region
4
is formed. The n
−
-type semiconductive region
20
extends from the n
+
-type semiconductive region
6
toward the first p-type semiconductive well region
3
, also referred to as the overflow barrier region
3
, and functions as a charge collecting region. The region in the photo-sensing area
5
which performs photoelectric conversion comprises the n
+
-type semiconductive region
6
and the n
−
-type semiconductive region
20
which is a portion of a depletion region extending downwardly from the n
+
-type semiconductive region
6
toward the substrate and which is a portion above the overflow barrier region
3
.
An n-type buried transfer channel region
10
of a vertical transfer register
9
is formed in the high-resistance region
4
, at a position corresponding to one side of a row of photo-sensors. A read-out gate region
8
is provided between the vertical transfer register
9
and the photo-sensing area
5
. A second p-type semiconductive well region
11
is formed to surround the buried transfer channel region
10
. A p-type channel stop region
12
is formed to separate pixels each of which includes the photo-sensing area
5
.
On the buried transfer channel region
10
, the channel stop region
12
, and the read-out gate region
8
, a transfer electrode
15
comprising, for example, polycrystalline silicon, is formed with a gate insulating layer
14
therebetween. The buried transfer channel region
10
, the gate insulating layer
14
, and the transfer electrode
15
constitute the vertical transfer register
9
having a CCD structure. A light-shielding layer
17
of, for example, aluminum, is formed on an interlayer insulating layer
16
covering the transfer electrode
15
and over the entire region other than an opening of the photo-sensing area
5
.
An on-chip lens
19
for focussing incident light in the photo-sensing area
5
is formed at a position corresponding to each photo-sensing area
5
and is separated from thelight shielding layer
17
by a planarization layer
18
and a color filter (not shown).
In this CCD image sensor
1
, the region extending from the n
+
-type semiconductive region
6
to the n
−
-type semiconductive region
20
, i.e., the region which includes the n
+
-type semiconductive region
6
and the depletion layer extending from the n
+
-type semiconductive region
6
to the overflow barrier region
3
, performs photoelectric conversion and collects charge. Generally, much of the light entering the photo-sensing area
5
is oblique due to the on-chip lens
19
used for focussing.
An incident path of light L is shown in FIG.
7
. The light L entering the photo-sensing area
5
initially passes through the n
−
-type semiconductive region
20
of the photo-sensing area
5
. However, in the region under the transfer electrode
15
, although the overflow barrier region
3
is yet to be reached, the charge generated by the photoelectric conversion is drained to the substrate
2
without being accumulated in the n
+
-type semiconductive region
6
.
This is because the focussing structure for the photo-sensing area does not take into consideration the oblique rays entering the photo-sensing area
5
. Recently, the condensing rate has been increased by adding internal layer lenses, increasing the oblique rays. Under these circumstances, significant portion of the condensed light is discarded, causing the sensitivity to decrease.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a solid state image sensor with improved sensitivity, in which the charge obtained from oblique rays by photoelectric conversion is collected efficiently.
A solid state image sensor according to the present invention comprises a primary first-conductivity-type semiconductive region which serves as a charge storage region of a photo-sensing area, and a secondary first-conductivity-type semiconductive region, formed under the primary first-conductivity-type semiconductive region, for enlarging a charge collecting region of the photo-sensing area.
Because the secondary first-conductivity-type semiconductive region is provided under the primary first-conductivity-type semiconductor region serving as a charge storage region, the charge collecting region is enlarged horizontally and vertically. Thus, light entering the photo-sensing area at an oblique angle can also be collected and the sensitivity thereof can be efficiently enhanced.
Preferably, the secondary first-conductivity-type semiconductive region is larger than the photo-sensing area. In this configuration, the charge collecting region can be further expanded and the sensitivity can be improved.
Preferably, the solid state image sensor further comprises an isolation region for isolating the secondary first-conductivity-type semiconductive region. In this configuration, the depletion layer is inhibited from extending to the adjacent pixel, thereby preventing blooming.
REFERENCES:
patent: 4672455 (1987-06-01), Miyatake
patent: 5191399 (1993-03-01), Maegawa et al.
patent: 5446297 (1995-08-01), Lee
patent: 5514887 (1996-05-01), Hokari
patent: 5903021 (1999-05-01), Lee et al.
Munson Gene M.
Sonnenschein Nath & Rosenthal
Sony Corporation
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