Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-11-13
2003-11-18
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S678000
Reexamination Certificate
active
06649931
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electrical characteristic test technique for a semiconductor device and particularly to the technique that can be effectively adapted to the method of storing historical information of the burn-in test under the semiconductor wafer condition, so-called the wafer level burn-in in a semiconductor device such as MCP (Multi-Chip Package) mounting a couple of semiconductor chips, for example, a flash memory and SRAM.
FIELD OF THE INVENTION
Background Art
Following techniques have been proposed for the semiconductor device burn-in test as the technique which the inventors of the present invention have investigated. For example, the burn-in process of MCP mounting a flash memory and SRAM is generally conducted in the manner that the temperature and voltage stress exceeding the rating are applied in the testing process in which the semiconductor chips of the flash memory and SRAM are mounted on a substrate and these are electrically connected with the wire bonding method and are then molded with a resin to assemble the package structure. With this burn-in process, MCP having probability of a future fault is screened and only the good MCP is good MCP is delivered as a product.
As the technique for the pretest before the wafer test such as the burn-in test as explained above and the technique to store the wafer test result into a memory array, there are provided, for example, the techniques described in Japanese Unexamined Patent Publication Nos. HEI 8(1996)-23016 and HEI 6(1994)-5098. The technique described in the Japanese Unexamined Patent Publication No. HEI 8(1996)-23016 is proposed to store the information about good or defective products of the pretest into the redundant area of memory or to the particular area of the normal memory in order to reduce the next wafer test time. The technique described in the Japanese Unexamined Patent Publication No. HEI 6-5098 proposes the write operation of electrical characteristic during the wafer test to the redundant memory.
SUMMARY OF THE INVENTION
Here, investigation by the inventors of the present invention for the MCP burn-in technique explained above has made apparent that since the yield of the semiconductor chips of the flash memory and SRAM gives large influence on the yield of MCP after the assembling and therefore it is difficult to expect the improvement in the yield of MCP in the method of burn-in after the assembling of MCP as explained above. Namely, when this method is employed, if a fault is generated in any one of the semiconductor chips of flash memory and SRAM, the MCP assembled using these elements also becomes a fault and therefore it is thought that the yield of assembled element is deteriorated.
Therefore, the inventors of the present invention have found a method to redundantly relieve or reject semiconductor chips of defective products before the assembling by conducting the wafer level burn-in under the semiconductor wafer condition in order to improve the yield of the semiconductor chips of the flash memory and SRAM. In this case, for example, like the assembled products, each probe connected to the testing apparatus is placed in contact with each terminal of the semiconductor chip, electrical conductivity is checked between each probe in the contact condition and each terminal and thereafter the screening can be realized by executing the erase/write mode and the read mode.
However, in such wafer level burn-in, it is probable that a problem of time is generated and defective product is leaked to the assembling process because the probe test is executed to all chips including the chip found as a defective product in the burn-in test after such a wafer level burn-in test is completed. Moreover, it is also though as a problem that analysis for the cause of fault when a fault is generated in the product after the assembled products are delivered to customers.
In the techniques described in the Japanese Unexamined Patent Publication Nos. HEI 8(1996)-23016 and HEI 6(1994)-5098, the result of pretest before the wafer test and the result of the wafer test are stored in the memory array and these techniques are different from the technique for storing the historical data of the wafer level burn-in which is conducted in the semiconductor wafer condition just like the present invention.
It is therefore an object of the present invention to provide an electrical characteristic testing technique of a semiconductor device that can reduce the probe testing time, prevent leakage of defective products into an assembling process and moreover easily realize analysis of cause of generation of defective products after the delivery to customers by storing the historical data of this wafer level burn-in while the wafer level burn-in process is introduced.
The abovementioned and the other objects and novel features of the present invention will become more apparent from the description of the present specification and the accompanying drawings.
Typical inventions among those disclosed in the present specification can be briefly summarized as follows.
(1) A semiconductor wafer of the present invention mounts a plurality of semiconductor chips each of which also includes a non-volatile memory array, wherein said semiconductor chip comprises a first memory area for storing input information of usual operation and a second memory area for storing historical information of an electrical characteristic test of the first memory area. Moreover, in this semiconductor wafer, the electrical characteristic test is also adapted to the wafer level burn-in test. In addition, the second memory area may be adapted to the flash fuse area and OTP area or the lock bit area of the non-volatile memory area. Otherwise, the second memory area can be adapted to a part of the first memory area of the non-volatile memory area.
(2) The semiconductor chip of the present invention has a non-volatile memory array including a first memory area for storing an input information of usual operation and a second memory area for storing the historical information of the electrical characteristic test of the first memory area. Moreover, in the semiconductor chip, the electrical characteristic test is adapted to the wafer level burn-in test.
(3) The semiconductor device of the present invention mounts a semiconductor chip comprising a first memory area for storing input information of usual operation and a second memory area for storing historical information of an electrical characteristic test of the first memory area. Moreover, in the semiconductor device explained above, the electrical characteristic test can be adapted to the wafer level burn-in test.
(4) The other semiconductor device of the present invention mounts a first semiconductor chip including a non-volatile memory array comprising a first memory area for storing input information of usual operation and a second memory area for storing historical information of an electrical characteristic test of the first memory area and a second semiconductor chip including a non-volatile memory array comprising a third memory area for storing an input information of usual operation, thereby for storing historical information of an electrical characteristic test of the third memory area of the second semiconductor chip in the second memory area of the first semiconductor chip. Moreover, the electrical characteristic test is adapted to the wafer level burn-in test in the other semiconductor device explained above.
(5) A method of manufacturing a semiconductor device of the present invention is adapted to a semiconductor device mounting a semiconductor chip having a non-volatile memory array cut out from a semiconductor wafer, comprising a process to conduct an electrical characteristic test of a first memory area for storing input information of usual operation of the semiconductor chip before cutting out the semiconductor chip from the semiconductor wafer and a process to store historical information of the electrical characteristic test to the second memory area
Haruyama Katsuhiro
Hatazawa Takahiro
Honma Kazuki
Kitajima Fumiaki
Motomatsu Hiroyuki
Hitachi , Ltd.
Miles & Stockbridge P.C.
Nhu David
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