Method of estimating time delay

Details Method of estimating time delay Method of estimating time delay

2000-11-17

2003-02-04

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06516454

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of estimating a time delay caused by one of multiple cells, including logic elements, in a semiconductor integrated circuit.
To reduce the power dissipated by a semiconductor integrated circuit or to increase the operating speed thereof, a supply voltage to be applied to the circuit sometimes needs to be changed selectively. This is because if the supply voltage is changed, then a signal will be propagated through the circuit at a different rate and eventually the power consumed by the circuit will be changeable also. However, once the supply voltage is replaced with a newly selected one, the circuit will cause a different amount of time delay. Thus, it is necessary for the designer of the circuit to know the time delay that will be estimatingly caused by the circuit upon the application of the selected voltage. And then the designer needs to make sure whether or not the circuit still can operate normally even if the circuit should cause the time delay in that estimated amount.
Generally speaking, while a circuit is being laid out, a time delay caused by each of the cells for the circuit can be represented as a function of the transition time of a signal wave input to the cell and the capacitance of a load driven by the cell. The function may be represented by either a table indexed by transition time and load capacitance or an equation that also uses transition time and load capacitance as arguments. Although each of these methods has its own advantages and disadvantages, the former table method is usually preferred because the time delay can be represented much more freely than the other. It should be noted that tables such as those illustrated in
FIG. 3
will be herein called “delay tables”.
In representing a circuit's time delays as a delay table, if there are two or more supply voltages applicable to the circuit, then the same number of delay tables should be prepared. That is to say, one delay table needs to be provided for each supply voltage. Each of those delay tables can be compiled from time delays, which were measured as representative values for a combination of transition times and load capacitances through circuit simulations. As used herein, the combination of transition times and load capacitances, from which a delay table is compiled, will be called “delay table indices”. Accordingly, to newly compile a delay table, the time delays caused by each cell need to be measured by performing simulations on the circuit. Thus, it takes a great deal of man-hour to prepare a delay table for each and every supply voltage to be applied.
A technique of eliminating this problem is proposed in Japanese Laid-Open Publication No. 11-3366, for example. According to the technique, a reference time delay is calculated using a combination of circuit operation conditions, including predefined supply voltage, process variation and temperature, as a reference combination. Next, a coefficient table is prepared. On this table, various time delay coefficients, corresponding to respective combinations of circuit operation conditions (which are determined by multiple combinations of variable elements prepared for the reference time delay), are stored. And by multiplying the reference time delay by a time delay coefficient associated with a given combination of circuit operation conditions, a time delay, which will be caused under the given conditions, is obtained for each cell. In this manner, the technique makes it possible to obtain an estimated time delay associated with a target supply voltage without compiling any new delay table.
However, the present inventors found out based on results of experiments that the variation of time delay against supply voltage is actually not uniform but changeable among respective cells (i.e., depending on the type of a cell in question). For that reason, according to the technique disclosed in the above-identified publication, the time delay estimated almost always contains a certain amount of error, because the same coefficient is applied to each and every cell irrespective of its type. As a result, the time delay associated with the given supply voltage cannot be estimated accurately enough by such a method. And we found that the variation of time delay against supply voltage is changeable among cells because the threshold voltages of the cells are different from each other.
Hereinafter, it will be described with reference to
FIGS. 19 and 20
specifically how the difference in threshold voltage of cells affects the time delays of the cells. In
FIGS. 19 and 20
, IN denotes the waveform of a signal input to a given cell, OUT denotes the waveform of the output signal of the cell, and Vth
101
denotes a threshold voltage used as a reference voltage in estimating the time delay. It should be noted that the threshold voltage Vth
101
is defined for convenience sake only and is different from the threshold voltage specific to an individual cell. As used herein, the “threshold volt age” of a cell refers to a voltage at which a signal level transition starts to be propagated to the next stage. Accordingly, when cells designed are actually implemented, the threshold voltage is variable among those cells. Also, even in a single cell, if the cell has two or more input terminals, then the threshold voltage is also variable among the input terminals. And the threshold voltage is changeable as well depending on the voltage of signal input. In the known methods, however, the threshold voltage is supposed to be constant due to various constraints involved with a CAD tool. As shown in
FIG. 19
, the time delay T
101
of a cell is herein defined as an interval between the instant the level of the input signal wave IN reaches the threshold voltage Vth
101
and the instant the level of the output signal waveform OUT reaches the threshold voltage Vth
101
. Suppose a signal wave IN
11
has been presented to a predetermined input terminal. Then, as shown in
FIG. 20
, the actual threshold voltage at the input terminal will be Vth
112
and Vth
113
for supply voltages V
1
and V
2
, respectively. It should be noted that the voltages Vth
2
and Vth
113
are herein normalized with the supply voltages V
1
and V
2
, respectively. In this case, if the supply voltage has changed from V
1
into V, then the threshold voltage will also change from Vth
112
into vth
113
and the time delay T
101
will also change by the lag T
114
. The time lag T
114
only reflects the variation in threshold voltage. Accordingly, the time delay T
101
is actually further variable depending on a variation in drivability as well.
As can be seen, the time lag T
114
is variable among individual cells or among respective input terminals in a cell. In spite of this fact, if the same combination of circuit operation conditions is applicable, the same coefficient is automatically used for each and every cell according to the known delay estimating method. Thus, such a technique cannot take a variation in delay, resulting from the time lag T
114
, into account.
FIG. 21
illustrates respective ratios of time delays, resulting from various supply voltages applied to five types of cells, to a reference time delay associated with a reference supply voltage of 2.5 V. As shown in
FIG. 21
, the supply voltage applied was changed between 1.8 V and 2.7 V at a scale of 0.1 V and the time delays were estimated through circuit simulations. In this case, the cells used were inverter, five-input NAND gate, five-input NOR gate, buffer, five-input AND gate and five-input OR gate. The ratios were also obtained for the rise and fall of the output signal waveform of each cell. As can be seen from
FIG. 21
, the time delay obviously changes depending on the type of a cell.
FIG. 22
illustrates respective ratios of time delays, caused by an inverter at ten different supply voltages, to a reference time delay associated with a reference supply voltage of 2.5 V. In the example illustrated in
FIG. 22
, the inverter was operated under nine different co

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