Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-11
2003-02-25
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S623000, C438S624000
Reexamination Certificate
active
06524948
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having multi-layer wires and a method for fabricating the same. More particularly, it relates to the structure of a plug for connecting a lower-layer wire having an air gap in a wire-to-wire space to an upper-layer wire and to a method for forming the same.
As semiconductor devices have become higher in integration and performance in recent years, wires in the semiconductor devices have increasingly been reduced in size and placed in multiple layers. The size reduction and multilayer placement of the wires increases a wire-to-wire capacitance, which adversely affects the operating speed of a semiconductor element. To prevent this, a method of scaling down the wires or placing the wires in multiple layers, while reducing the wire-to-wire capacitance, has been required.
To reduce the wire-to-wire capacitance, an insulating material with a low relative dielectric constant may be used for an interlayer insulating film. To further reduce the wire-to-wire capacitance, an air gap may also be formed in a wire-to-wire space (region lying between a pair of adjacent wires).
Referring to the drawings, a description will be given herein below to a conventional method for fabricating a semiconductor device as disclosed in technical papers by T. Ueda et al. ((1) A Novel Air Gap Integration Scheme for Multi-level Interconnects using Self-aligned Via Plugs: 1998 Symposium on VLSI Technology Digest of Technical Papers, P.46, 1998., (2) Integration of 3 Level Air Gap Interconnect for Sub-quarter Micron CMOS: 1999 Symposium on VLSI Technology Digest of Technical Papers, P.111, 1999, and the like), specifically a method for forming multilayer wires having air gaps.
FIGS. 8A
to
8
C,
FIGS. 9A
to
9
C, and
FIGS. 10A
to
10
C are cross-sectional views illustrating the individual process steps of the conventional method for fabricating a semiconductor device.
First, as shown in
FIG. 8A
, an underlying insulating film
11
composed of a silicon dioxide, a first conductive film
12
composed of an aluminum alloy with a thickness of 600 nm, and a first interlayer insulating film
13
composed of a silicon dioxide with a thickness of 1500 nm are deposited successively on a semiconductor substrate
10
composed of silicon. Then, a mask pattern
14
having an opening corresponding to a region to be formed with a plug is formed on the first interlayer insulating film
13
.
Next, etching is performed with respect to the first interlayer insulating film
13
by using the mask pattern
14
, thereby forming a connection hole
15
reaching the first conductive film
12
and having a diameter of about 400 nm, as shown in FIG.
8
B. Thereafter, the mask pattern
14
is removed.
Next, a second conductive film composed of tungsten is deposited by vapor deposition or the like over the entire surface of the first interlayer insulating film
13
including the connection hole
15
such that the connection hole
15
is filled fully with the second conductive film. Then, the portion of the second conductive film located externally of the connection hole
15
is polished away by CMP (chemical mechanical polishing), whereby a plug
16
connected to the first conductive film
12
is formed, as shown in FIG.
8
C.
Next, as shown in
FIG. 9A
, the first interlayer insulating film
13
is etched back to have a thickness of about 300 to 600 nm such that an upper portion of the plug
16
protrudes from an upper surface of the first interlayer insulating film
13
. This effects control of the position of a top portion of each of air gaps
20
(see FIG.
10
A), which will be formed in the subsequent step.
Next, as shown in
FIG. 9B
, a resist pattern
17
covering a region to be formed with a lower-layer wire is formed on the first interlayer insulating film
13
.
Next, as shown in
FIG. 9C
, etching is performed sequentially with respect to the first interlayer insulating film
13
and the first conductive film
12
by using the resist pattern
17
and the plug
16
as a mask, thereby forming a lower-layer wire
12
A composed of the first conductive film
12
and connected to the plug
16
.
In the step illustrated in
FIG. 9C
, etching is also performed with respect to the underlying insulating film
11
by using the resist pattern
17
and the plug
16
as a mask after the formation of the lower-layer wire
12
A, thereby removing the surface portions of the underlying insulating film
11
located under the wire-to-wire spaces of the lower-layer wire
12
A to a depth of about 300 nm.
Next, the resist pattern
17
is removed. Then, as shown in
FIG. 10A
, a second interlayer insulating film
18
composed of a silicon dioxide, which is high in directivity and low in coverage rate, and having a thickness of about 200 to 500 nm is deposited over the entire surface of the semiconductor substrate
10
by plasma CVD using silane gas and dinitrogen oxide gas. Subsequently, a third interlayer insulating film
19
composed of a silicon dioxide having an excellent burying property and a thickness of about 1000 nm is deposited by high-density plasma CVD, whereby the air gaps
20
are formed in the wire-to-wire spaces of the lower-layer wire
12
A.
Next, as shown in
FIG. 10B
, the second interlayer insulating film
18
and the third interlayer insulating film
19
are polished by CMP till the plug
16
is exposed such that the respective upper surfaces of the second and third interlayer insulating films
18
and
19
are planarized to be flush with the upper surface of the plug
16
.
Next, as shown in
FIG. 10C
, an upper-layer wire
21
is formed over the planarized second and third interlayer insulating films
18
and
19
to be connected to the plug
16
, whereby a two-layer wire structure is completed.
Thus, the conventional method for fabricating a semiconductor device has formed the plug
16
for electrically connecting the lower-layer wire
12
A and the upper-layer wire
21
prior to formation of the lower-layer wire
12
A and then formed the lower-layer wire
12
A by patterning the first conductive film
12
by using the plug
16
as a mask. This prevents displacement between the plug
16
and the lower-layer wire
12
A and thereby improves the reliability of the multilayer wires.
To lower the positions of the respective top portions of the air gaps
20
formed in the wire-to-wire spaces of the lower-layer wire
12
A, however, the conventional method for fabricating a semiconductor device has etched back the first interlayer insulating film
13
such that the upper portion of the plug
16
protrudes from the upper surface of the first interlayer insulating film
13
, as shown in FIG.
9
A. Consequently, the resist pattern
17
is formed on the rugged underlie, as shown in FIG.
9
B. As a result, the accuracy of pattern exposure is lowered and the resist pattern
17
may be deformed or the formed resist pattern
17
may partly collapse, which renders the size reduction of the resist pattern
17
difficult and renders the scaling down of the lower-layer wire
12
A, i.e., the multilayer wires difficult.
If the plug
16
is formed to have an upper portion not protruding from the upper surface of the first interlayer insulating film
13
, the top portion of the air gap
20
may reach a height equal to the height of the upper surface of the plug
16
. In this case, the air gap
20
has an opening formed in the upper surface of the planarized second interlayer insulating film
18
or third interlayer insulating film
19
in the polishing step performed with respect to the second interlayer insulating film
18
and the third interlayer insulating film
19
(see
FIG. 10B
) so that the conductive film serving as the upper-layer wire
21
enters the opening. This causes a formation defect such as a breakage in the upper-layer wire
21
and reduces the reliability of the multilayer wires.
With the increasing miniaturization of semiconductor devices, there are a growing number of cases where plugs connecting lower-layer and upper-layer wires have been placed
Nakagawa Hideo
Tamaoka Eiji
Nixon & Peabody LLP
Studebaker Donald R.
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