Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-06
2003-02-18
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S303000
Reexamination Certificate
active
06521934
ABSTRACT:
This application is based on Japanese Patent Application 2000-093672, filed on Mar. 28, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to semiconductor devices and their manufacture methods, and more particularly to semiconductor techniques of forming different elements on the same substrate, the elements including DRAM memory cells and SRAM memory cells with MOSFET's, and analog capacitors and flash memories.
b) Description of the Related Art
In this specification, an offset insulating film is intended to mean an insulating film (cap layer) formed on a conductive layer and having the same shape as viewed in plan as that of the conductive layer. The conductive layer may have a multi-layer structure or the offset insulating film may have a multi-layer structure. In this specification, the terms “lamination structure” or “lamination structural body” are intended to mean a structural body including a lamination structure (structural body) of an electrode and an insulating film such as an offset film formed on the electrode. An element region is intended to mean a region containing at least one active region therein. The principal surface of a semiconductor substrate is a two-dimensional surface and its surface irregularity such as concave and convex poses almost no practical problem. A “height” is intended to mean a height measured from such a two-dimensional surface along a direction normal to the surface.
Recent large scale of semiconductor integration circuits requires micro-fine semiconductor elements. In order to realize a semiconductor integrated circuit having gate electrodes, wirings and contact holes more smaller in size, resolution of photolithography has been improved heretofore by using exposure light of a shorter wavelength.
Device structures have been studied which can reduce a minimum image resolution size as well as a position alignment margin between lithography processes. As one example of such device structures, a self-align contact (hereinafter called SAC) structure is known.
FIG. 7
is a cross sectional view showing the outline structure of SAC.
As shown in
FIG. 7
, an element isolation region
501
is defined in a silicon substrate
500
. A number of lamination structural bodies G
1
are formed on the silicon substrate
500
on the element isolation region
501
and in an area away from the region
501
by some distance. The lamination structural body G
1
is formed on a gate insulating film
503
and has the lamination structure made of a gate electrode layer
505
, a barrier metal layer
507
and an offset insulating film
511
. In the following description, a lamination of the gate electrode layer
505
, barrier metal layer
507
and offset insulating film
511
is called the lamination structural body G
1
. Spacer films (side wall insulating films)
515
are formed on the side walls of the lamination structural body G
1
.
Contact holes are formed between mutually adjacent lamination structural bodies G
1
, being sandwiched between the spacer films
515
formed on the side walls of the lamination structural bodies G
1
. In each contact hole, a plug electrode
521
of doped amorphous silicon is formed. The bottom surface of the plug electrode
521
is in contact with the surface of the silicon substrate
500
. The plug electrode
521
connects together, for example, an upper structure to be formed above the lamination structural body G
1
and a lower structure to be formed in the silicon substrate
500
.
The upper surface of the plug electrode
521
can be made generally flush with the upper surface of the offset insulating film
511
, for example, by a chemical mechanical polishing (CMP) method.
If SAC techniques are incorporated, the plug electrode
521
can be formed in a self alignment manner between adjacent lamination structural bodies G
1
. A position alignment margin can therefore be increased between a contact hole forming process and a plug electrode forming process.
With developments on semiconductor integrated circuit techniques, it is possible to realize a so-called system LSI in which one or more systems are formed in one semiconductor chip by forming various types of integrated circuits. A system LSI has various types of IC's formed therein, including a logic IC cell part, a memory cell part (such as dynamic random access memory (DRAM), static random access memory (SRAM) and flash memory), an analog cell part and the like. In order to form such various IC's and reduce an area occupied by these IC's, SAC techniques are becoming more and more important. It is an important point that micro-fineness and high reliability of a system LSI rely on how the heights of upper surfaces of offset insulating films are made flush in respective IC's in the silicon substrate plane.
Problems which occur when a memory cell part and an analog cell part are formed on the same substrate will be described with reference to FIGS,
8
A to
8
E, by taking as examples a DRAM cell part and an analog capacitor part.
As shown in
FIG. 8A
, first and second element regions
400
a
and
400
b
are defined in a silicon substrate
400
. In the first element region
400
a
, a DRAM cell part is formed having a number of lamination structural bodies (word lines) G
1
. The structure of the DRAM cell part is similar to the SAC structure shown in FIG.
7
. In the second element region
400
b
, an analog capacitor part is formed having an analog capacitor element Cp.
A gate oxide film
403
is formed on the surface of the first element region
400
a
. On the gate oxide film
403
, a first lamination structural body G
1
is formed including a lamination of a gate electrode layer
405
a
, a barrier metal layer
407
a
and an offset insulating film
411
a
. Spacer films (side wall insulating films)
415
a
are formed on the side walls of each lamination structural body G
1
.
The analog capacitor element Cp formed in the second element region
400
b
includes a lower electrode
430
, a dielectric layer
429
and a second lamination structural body. The second lamination structural body has a three-layer structure including an upper electrode
405
b
, a barrier metal layer
407
b
and an offset insulating film
411
b
. Spacer films
415
b
are formed on the side walls of the lower electrode
430
, dielectric layer
429
and second lamination structural body. The gate electrode layer
405
a
, barrier metal layer
407
a
and offset insulating film
411
a
are formed by the common layers to those of the upper electrode
405
b
, barrier metal layer
407
b
and offset insulating film
411
b.
The height of the upper surface of the offset insulating film
411
b
in the analog capacitor part as measured from the upper surface of the silicon substrate
400
is higher than the height of the upper surface of the offset insulating film
411
a
in the DRAM cell part by an amount corresponding to a thickness of the lower electrode
430
and dielectric layer
429
(both collectively called a lower structure).
Interlayer insulating films
410
a
and
410
b
are formed over the silicon substrate
400
, covering the lamination structural bodies G
1
and analog capacitor element Cp and having the etching characteristics different from the offset insulating films
411
a
and
411
b
. Although the interlayer insulating film
410
a
is formed in the first element region
400
a
and the interlayer insulating film
410
b
is formed in the second element region
400
b
, these interlayer insulating films are made of the same layer. The upper surface of the interlayer insulating film
410
a
is lower than the upper surface of the interlayer insulating film
410
b
. Under the etching conditions that the interlayer insulating films can be selectively etched relative to the offset insulating films, the interlayer insulating films
410
a
and
410
b
are polished from their upper surfaces by CMP. CMP automatically stops when the upper surface of the offset insulating film
411
b
is
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Pham Hoai
Pham Long
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