Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
1998-09-18
2003-02-25
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S111000, C711S167000
Reexamination Certificate
active
06526471
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of computer system design. In particular the present invention discloses a high-speed memory subsystem that quickly responds to processor memory requests.
BACKGROUND OF THE INVENTION
Early microprocessors (such as early 8-bit microprocessors) executed instructions fetched directly from a main memory. However, modern microprocessors now operate at speeds much faster than main memory can provide instructions. To accommodate the faster microprocessors, high-speed cache memory was added in between the main memory and the microprocessor. A cache memory may be internal (on the same die as the processor) or external (not on the same die as the processor). The high speed cache memory duplicates information stored in the main memory.
A cache controller is used to control processor accesses to the cache memory. If the cache controller that the cache memory does not contain a copy of a requested memory location, then the cache controller directs the memory request to the slower main memory. Accesses to a main memory are handled by a memory controller. Memory controllers perform a number of different functions. Memory controllers may handle memory interleaving, DRAM memory refreshing, and memory precharging.
To interface a relative slow main memory to faster microprocessor, a memory controller may latch information from the fast processor's memory request and then relay the memory request to the slow main memory. Specifically, to respond to a read request to main memory, the memory controller latches the requested memory address and then strobes a row and column address in the main memory. After the main memory returns a data value, the memory controller relays the data value back to the processor to respond to the processor's read request. During the steps of latching the read address, strobing the row and column addresses, and waiting for the main memory response, the processor remains idle. The multi-step process of accessing main memory through a standard memory controller significantly slows non-cache memory accesses. It would therefore be desirable to design a memory control system that accesses main memory in a more efficient manner.
SUMMARY OF THE INVENTION
A high speed memory control system is disclosed. The memory system of the present invention stores the active n memory rows for m banks of memory. When a memory access request for a memory address that falls within one of the active memory rows is received, the memory controller immediately responds to the memory access request. When a memory access request for a memory address that does not fall within one of the active memory rows is received, the memory controller immediately precharges the desired memory address. For read operations, the memory controller responds with the data from the requested memory address after the memory has been precharged. For memory write operations, the memory controller forces the processor to halt its memory write request.
Other objects feature and advantages of present invention will be apparent from the company drawings and from the following detailed description that follows below.
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Peting Mark
Shimomura Tsutomu
Chace C. P.
Digeo, Inc.
Kim Matthew
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