Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-01-07
2003-10-28
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S207000, C365S189090
Reexamination Certificate
active
06639852
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a sensing apparatus for a ROM memory device, and more particularly, to a sensing apparatus for a ROM memory device to determine the logical value of a selected ROM memory cell by reading its current output.
BACKGROUND OF INVENTION
Read-only memories or ROMs are used to store non-volatile data in digital devices, and, in particular data storage for microprocessor-based computer systems. As electronic devices become smaller in size, they become more dependent on data storage and the amount of data needed to be stored is increased. ROM devices can include non-programmable ROM's such as mask ROMs, and programmable ROMs such as EPROMs, EEPROMs, or Flash EPROMs.
Typically a ROM is divided into a plurality of memory cells, which are arranged into matrices. Each individual memory cell can be accessed using two signal lines typically referred to as a bitline and a wordline. Programming of the ROM devices as to assign each memory cell a logic value is accomplished by defining the threshold voltage of a field effect transistor structure in the memory cell. When a minimum amount of voltage is applied to the gate of the transistor structure, the transistor turns on and permits a current flow between a source and drain regions. Oppositely if a memory cell is not programmed, a different voltage is applied to the gate of the transistor to remain turned off. A read circuit or circuits are connected to the ROM cell matrix to determine what logical value a memory cell represents.
A typical ROM memory apparatus is shown in
FIG. 1
a
. ROM memory cells are addressed by activating the associated wordline and column select line in a memory cell. A voltage source is connected to a first end of the bit line. Transistor
11
is programmable with a reference voltage threshold, transistor
12
is an unprogrammed transistor, and transistor
13
is a programmable memory cell.
FIG. 1
b
shows a voltage-time chart corresponding to the voltages on transistors
11
,
12
, and
13
. When unprogrammed transistor
12
is selected, the transistor will remain turned off when its wordline is selected. Therefore a voltage close to VCC will be applied to input A of the voltage sense amplifier. When transistor
13
is selected and programmed, it will turn on when the wordline is at its specified voltage threshold. This will cause the voltage on its bitline to be reduced accordingly when it is applied to input A of the voltage sense amplifier. Transistor
11
has been programmed with a reference threshold level. When the transistor is selected, it will turn on at a specified voltage threshold, and it will change the voltage of the bitline accordingly. When the output voltage is applied to the input B of the voltage sense amplifier, the transistor
11
will change the voltage in the bitline. The voltage sense amplifier has a delay waiting to compare the voltages before a difference on the bit lines develops. After the delay, the voltage sense amplifier will compare the inputted voltage with the reference voltage and amplify the difference according to the logic value of the selected memory cell.
As the circuit size increases, and more high speed designs are implemented, large bit line capacitance and small cell current become significant problems. A long time period is required for a differential voltage to be established for an accurate output. Equivalently, the capacitive load is related to such factors as the condition of the cells around the bit lines, and their geometric configuration. Therefore a reading method that is not affected by bit line capacitance is needed.
SUMMARY OF THE INVENTION
An object of the invention provides a simple read circuit that can perform quick read operations for a ROM device.
Another objective of the invention is to provide a ROM memory cell read circuit that is not affected by bit line capacitance.
In accordance with the foregoing and other objectives, the invention proposes a ROM sensing apparatus comprising a plurality of memory cells and a decoder for selecting one of the memory cells. The ROM sensing apparatus further comprises a current conveyor having a first end for receiving a current from the selected memory cell and a second end for receiving a reference current, and a current differential sense amplifier coupling to the current conveyor. The current differential sense amplifier is for comparing the current from the selected memory cell and the reference current and amplifying the difference between the two currents.
In accordance with the foregoing and other objectives, the invention proposes an apparatus for sensing a ROM memory device, in which the ROM memory device having a plurality of memory cells and having a plurality of decoders for selecting one of the memory cell. The apparatus comprises a current conveyor having a first end for receiving a current from the selected memory cell and a second end for receiving a reference current, and a current differential sense amplifier coupling to the current conveyor. The current differential sense amplifier is for comparing the current from the selected memory cell and the reference current and amplifying the difference between the two currents.
The invention provides a current source that is connected to one end of a bit line. A ROM memory cell is selected by the word line and column select line. The ROM memory cell can be programmed or not programmed. In the case of a programmed memory cell, when the wordline turns on a transistor in a selected ROM memory cell, a conducting current is passed through the bitline. A current level at the end of the bitline will therefore be equal to the source current subtract the current drawn out by the selected transistor. In the case of a non-programmed memory cell, when the wordline turns on, the selected non-programmed transistor will remain off. Therefore the current level outputted from the bitline will equal the source current. The bitline outputted current level is inputted to a current conveyer according to a reference current, and the current conveyor transfers the current levels to a differential sense amplifier. The sense amplifier compares a memory cell output current with a reference current and determines the logic level of the selected memory cell.
REFERENCES:
patent: 4648074 (1987-03-01), Pollachek
patent: 5386158 (1995-01-01), Wang
patent: 6115285 (2000-09-01), Montanari et al.
patent: 6205073 (2001-03-01), Naji
patent: 6259622 (2001-07-01), Fried et al.
patent: 6407589 (2002-06-01), Wei et al.
patent: 6445612 (2002-09-01), Naji
Faraday Technology Corp.
J. C. Patents
Le Thong
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