Completion unit register file using virtual addresses with quali

Details Completion unit register file using virtual addresses with quali Completion unit register file using virtual addresses with quali

1997-06-23

1999-02-23

Lane, Jack A.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711203, G06F 1200

Patent

active

058754830

ABSTRACT:
A method and apparatus for generating a qualify bit and detecting matching addresses in the completion unit register file, or annex, of a processor. A qualify bit is appended to each entry in the annex. Overlapping register windows are represented by a window pointer and a register index. Annex entries addressed to the same window or addressed to GLOBAL registers always qualify. Annex entries addressed to OUT registers only qualify if the instruction address is one of the IN registers of the next window. Annex entries addressed to IN registers only qualify if the instruction address is one of the OUT registers of the previous window. A pseudo-address bit is appended to each annex entry. For IN and OUT registers, the indexes for the aliases differ by one bit. The pseudo-address bit normally takes on the value of the most significant bit of the annex entry's index. If the instruction operand virtual register is an OUT register of a certain window, and the annex virtual register is an IN register within the next window, the pseudo-address bit for that entry is set to one. If the instruction operand virtual register is an OUT register within the previous window, the pseudo-address bit for that entry is set to zero. Comparison logic then compares the instruction operand index to the annex index with the differing bit of the annex index replaced by the pseudo-address bit. Entries that match and that have asserted qualify bits address the same physical register.

REFERENCES:
patent: 5237671 (1993-08-01), Freitas et al.

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