Semiconductor device

Details Semiconductor device Semiconductor device

2002-02-12

2003-11-11

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S408000

Reexamination Certificate

active

06646295

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor device and method for manufacturing the same and more particularly to a semiconductor device that may include a high breakdown-voltage transistor and a method for manufacturing the same.
BACKGROUND OF THE INVENTION
A semiconductor device, such as a non-volatile semiconductor memory device using non-volatile memory cells, can require high voltages to program or erase data in a memory cell. Thus, transistors that can withstand a high voltage are needed.
One such example of a conventional high breakdown-voltage transistor is disclosed in Japan Patent Publication No. 2000-299390 and illustrated in FIG.
8
.
Referring now to
FIG. 8
, a cross-sectional diagram of a conventional high breakdown-voltage transistor is set forth and given the general reference character
800
.
Conventional high breakdown-voltage transistor
800
is a MOSFET (metal oxide semiconductor field effect transistor). Conventional high breakdown-voltage transistor
800
is formed in an element region defined by an element isolation region
54
on a silicon substrate
48
. A gate electrode
52
is formed on the element region. A side-wall film
50
covers side surfaces of the gate
52
. A well is formed in the semiconductor substrate
48
. Incidentally, the boundary between the well and the semiconductor substrate
48
is not shown in FIG.
8
. Low concentration source/drain regions
58
and high concentration source/drain regions
56
are formed in the well. An intra-substrate high-concentration contour line
60
indicates a peak of the impurity concentration of the well in the vicinity of the high concentration source/drain regions
56
.
Conventional high breakdown-voltage transistor
800
can suffer from a decreased breakdown voltage as will now be explained.
First, there can be a large difference in silicon oxide film thickness of element isolation region
54
between ion implantation steps forming the well and the source/drain regions. Also, in a semiconductor device including complementary MOSFETs (CMOS) and non-volatile memory transistors (such as floating gate transistors), the thickness of a gate oxide film can vary greatly between the non-volatile memory transistors, a high break-down voltage transistor for controlling the non-volatile memory transistor, and CMOS transistors used for logic. To manufacture such a semiconductor device, gate oxidation and etching may be repeated many times. When a gate oxide film is etched, the silicon oxide film in an element isolation region (for example, element isolation region
54
) is typically etched simultaneously. However, ions are typically implanted to form a well before gate oxidation and ions are typically implanted to from source/drain regions after the gate oxidation process are completed. This results in a large difference in thickness of the silicon oxide film in the element isolation region
54
between when the well-forming ions are implanted and when the source/drain forming ions are implanted.
The above-mentioned difference in thickness of the silicon oxide film can be particularly problematic when the element isolation region
54
has a moderate slope near an element region end
62
. When an element isolation region
54
is formed by thermal oxidation at about 1100° C., the inclination of an element isolation region
54
may have such a moderate slope near the element region end
62
. Also, a trench may be formed under conditions that cause a moderate slope and may then be filled with a silicon oxide film to form element isolation region
54
having a moderate slope near the element region end
62
.
The reason why a sufficiently high breakdown voltage may not be obtained if the above-mentioned conditions occur will now be described with reference to FIG.
9
.
Referring now to
FIG. 9
, a cross section of conventional high-voltage transistor
800
in the vicinity of element region end
62
is set forth.
An upper surface of element isolation region
54
at the time of well-forming ion implantation is indicated by a broken line. At the time of source/drain forming ion implantation, the upper surface of element isolation region
54
is indicated by the solid line. The intra-substrate high-concentration contour line
60
produced in the substrate as a result of the well-forming ion implantation is indicated by a dot dashed line. The high concentration source/drain region
56
is indicated by another dashed line.
It is noted that due to the thick beveled shape of the element isolation region
54
at the time of well-forming ion implantation, the well tapers near the element region end
62
so that it is much more shallow. However, because the element isolation region
54
has a much thinner beveled shape at the time of the source/drain forming ion implantation, the high concentration source/drain region
56
does not taper as much, relative to the well. Due to this, a distance L
1
between the high concentration source/drain region
56
and the intra-substrate high-concentration contour line
60
in a central area is greater than a distance L
2
between the high concentration source/drain region
56
and the intra-substrate high-concentration contour line
60
near the element isolation region
54
. This results in a decrease in a breakdown voltage of conventional high-voltage transistor
800
.
Another conventional high-voltage transistor is disclosed in Japan Patent Application laid-Open No. Hei 8-181223 and illustrated in FIG.
10
.
In FIG.
10
(
a
), a cross-sectional diagram of a conventional high breakdown-voltage transistor is set forth and given the general reference character
1000
. In FIG.
10
(
b
), a plan view of conventional high-voltage breakdown transistor
1000
is set forth.
Referring now to FIG.
10
(
a
), conventional high-voltage breakdown transistor
1000
is a MOSFET. Conventional high breakdown-voltage transistor
1000
is formed in an element region defined by an element isolation region
114
on a silicon substrate
108
. The transistor
1000
includes a low concentration source/drain region
118
and a high concentration source drain region
116
, which are formed in a well, and a gate electrode
112
. An intra-substrate high-concentration contour line
120
indicates a peak of the impurity concentration of the well in the vicinity of the high concentration source/drain regions
116
.
In conventional high-voltage breakdown transistor
1000
, gate
112
is also disposed over the element region end
122
. This can prevent the high concentration source/drain region
116
from being formed at the element region end
122
, so that the distance between the high concentration source/drain region
116
and the intra-substrate high concentration contour line
120
may not be reduced near the element region end
122
.
Referring now to FIG.
10
(
b
), the layout of the gate
112
is illustrated. Gate
112
is disposed over the element region end
122
(FIG.
10
(
a
)). Thus, gate
112
is formed in a loop pattern. This can cause increased chip size as will be discussed below.
Referring now to
FIG. 11
, a schematic diagram of a circuit is set forth and given the general reference character
1100
.
Circuit
1100
includes transistors (T
1102
and T
1104
) connected in series. Transistor T
1102
has a control gate connected to receive input IN
1
and transistor T
1104
has a control gate connected to receive input IN
2
. Circuit
1100
may illustrate a common construction of transistors, such as high-voltage breakdown transistors in a semiconductor device, such as a non-volatile semiconductor memory device, as just one example.
Conventional high-voltage breakdown transistor
1000
, as illustrated in
FIG. 10
, cannot be arranged so that two transistors are arranged in series and sharing the same source/drain region. This is due to the gate
112
being disposed over the element region end
122
. In order to construct circuit
1100
with two conventional high-voltage breakdown transistors
1000
, two separate source/drain regions
116
must be used, one source/drain regio

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