Multi-processor system and method for controlling access to a pa

Details Multi-processor system and method for controlling access to a pa Multi-processor system and method for controlling access to a pa

1996-06-28

1999-02-23

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711145, 711150, 711152, 711207, 711208, 711168, G06F 1318

Patent

active

058754733

ABSTRACT:
In a multi-processor system, a page descriptor can be updated in a memory coupled to a processor without stopping operations of other processors. Each processor has a page descriptor comparator including a calculated address register which stores a physical page address for an address calculation, and an updated address register which stores a physical page address to be updated. The page descriptor comparator also has a reset page descriptor (RSTPD) mode register which indicates a mode of the processor, and a coincidence detector. If the RSTPD mode register is active, the coincidence detector detects coincidence between the calculated address register and the updated address register.

REFERENCES:
patent: 5075846 (1991-12-01), Reininger et al.
patent: 5522045 (1996-05-01), Sandberg
patent: 5524235 (1996-06-01), Larson et al.

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