Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-02-09
2003-12-30
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S734000, C257S750000, C257S635000
Reexamination Certificate
active
06670709
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, a wiring structure using a film with a low dielectric constant and a method of manufacturing the same.
2. Description of the Related Art
In accordance with the microminiaturization of semiconductor devices, multilayer interconnection becomes necessary. Also, in accordance with the lowering of the voltage and speedup of operation of semiconductor devices, a lowering of the dielectric constant of the interlayer insulation film becomes necessary. Particularly, in logic-system semiconductor devices, an increase in resistance and an increase in parasitic capacitance between wires due to the micro-wiring lead to lowering of the operation speed of the semiconductor devices, so that multilayer interconnection using a film with a low dielectric constant as an interlayer insulation film becomes necessary in accordance with the microminiaturization.
Reductions in the wiring widths and wiring pitches increase the aspect ratio of the space between wires as well as the aspect ratio of the wires themselves, and as a result, it imposes a great cost burden on the technology for forming micro wiring which are thin and long in the vertical direction and on the technology for embedding the space in the micro wiring with an interlayer insulation film, and increases the number of processes as well as makes the manufacturing process of the semiconductor device complicated.
Therefore, trench wiring technology (damascene technology) by which wiring trenches are formed in the interlayer insulation film and wiring materials are embedded in the wiring trenches by using the chemical-mechanical polishing (CMP) method attracts much attention. However, in the formation of wiring trenches or formation of via-holes, the formation of a CMP stopper film or an etching stopper film becomes necessary.
As such a stopper film, an insulation film is used, whose etching speed is different from that of the interlayer insulation film in which wiring trenches or via-holes are formed. Therefore, a technology for using an insulation film with a low dielectric constant as the interlayer insulation film and using a silicon nitride film (SiN film) or a silicon oxynitride film (SiON film) as the stopper film has been variously studied. Such a technology is disclosed in, for example, Japanese Patent Laid-open Publications No. Hei 10-116904 and No. Hei 10-229122.
A semiconductor device shall be described in which wiring is formed by the conventional dual damascene technology using a silicon nitride film or a silicon oxynitride film as a stopper film and using a Si—O-based coating film as an interlayer insulation film.
FIG. 1
is a sectional view showing the conventional semiconductor device having the dual damascene wiring, and FIG.
2
A through
FIG. 2G
are sectional views showing the manufacturing method for the semiconductor device in the order of the processes.
As shown in
FIG. 1
, protective insulation film
102
and first HSQ (hydrogen silsesquioxane) film
103
are successively formed on first wiring
101
formed from, for example, an aluminum-copper alloy. Etching stopper film
104
is deposited on this first HSQ film
103
. This etching stopper film
104
is a SiN film or a SiON film deposited by the chemical vapor deposition (CVD) method.
Then, second HSQ film
105
is formed on the etching stopper film
104
, and CMP stopper film
106
is further deposited on the second HSQ film
105
. This CMP stopper film
106
is a SiN film or a SiON film deposited by the CVD method as the etching stopper film
104
. Or, this CMP stopper film
106
may be a silicon oxide film deposited by the CVD method. Wiring trenches
108
and
108
a
are formed in a predetermined region of the second HSQ film
105
and CMP stopper film
106
, and the protective insulation film
102
at the bottom of the etching stopper film
104
, the first HSQ film
103
, and the wiring trench
108
are opened to form via-hole
107
reaching the surface of the first wiring
101
. Barrier layer
109
is formed on the inner wall of this via-hole
107
and wiring trenches
108
,
108
a
, and second wirings
110
and
110
a
are formed to cover the barrier layer
109
and embed in the via-hole
107
, wiring trench
108
, and wiring trench
108
a.
Next, the method of manufacturing a conventional semiconductor device which has dual damascene wiring shall be described. As shown in
FIG. 2A
, a first wiring
101
formed from an aluminum-copper alloy is formed on a semiconductor substrate (not shown). A silicon oxide film with a thickness of approximately 50 nm is deposited on this first wiring
101
by the plasma CVD method to form protective insulation film
102
. Then, a coating solution to become an HSQ film is applied on the entire surface, fired at approximately 200° C., and further subjected to heat treatment at approximately 400° C. in a diffusion furnace. The first HSQ film
103
with a thickness of 350 nm is thus formed.
Next, as shown in
FIG. 2B
, a silicon nitride film with a thickness of approximately 50 nm is deposited all over by the plasma CVD method. Etching stopper film
104
is thus formed on the first HSQ film
103
.
Then, as shown in
FIG. 2C
, second HSQ film
105
is formed on the etching stopper film
104
. The thickness of the second HSQ film
105
is approximately 500 nm, and the method of forming this film is the same as that for the abovementioned first HSQ film
103
.
Next, as shown in
FIG. 2D
, a silicon oxide film with a thickness of approximately 50 nm is deposited on the entire surface by the plasma CVD method. CMP stopper film
106
is thus formed on the second HSQ film
105
.
Next, as shown in
FIG. 2E
, first resist mask
111
is formed by the generally-known photolithography technique, and by using this first resist mask
111
as an etching mask, the CMP stopper film
106
, the second HSQ film
105
, the etching stopper film
104
, and the first HSQ film
103
are dry-etched in order. Via-hole
107
to expose the surface of the protective insulation film
102
is thus formed.
Next, as shown in
FIG. 2F
, second resist mask
112
having a wiring trench pattern is formed, and by using the second resist mask
112
as an etching mask, the CMP stopper film
106
and the second HSQ film
105
are dry-etched in order. Thus wiring trenches
108
,
108
a
are formed. At this time, a dry-etching gas and its material are selected so as to increase the etching selection ratio of the second HSQ film
105
and the etching stopper film
104
, that is, so as to make the etching speed of the second HSQ film
105
higher than that of the etching stopper film
104
.
The first HSQ film
103
is protected from being dry-etched by the etching stopper film
104
in the abovementioned etching process. In this process, the exposed protective insulation film
102
is simultaneously etched, and the via-hole
107
reaches the surface of the first wiring
101
.
Next, as shown in
FIG. 2G
, the second resist mask
112
is removed. Then, a thin tantalum nitride (TaN) film is deposited on the entire surface by means of spattering to form barrier layer
109
on the inner walls of the via-hole
107
and the wiring trenches
108
,
108
a
and on the surface of the CMP stopper film
106
. Subsequently, a seed Cu film with a thickness of approximately 50 nm is deposited by means of spattering, and Cu film
113
with a thickness of approximately 1000 nm is further deposited by means of plating.
Next, not illustrated, the Cu film
113
and the barrier layer
109
are subjected to the CMP. In this CMP process, the second HSQ film
105
is protected from CMP by the CMP stopper film
106
. The semiconductor device having the dual damascene wiring shown in
FIG. 1
is thus formed.
However, in the prior-art mentioned above, the dielectric constant of the etching stopper film becomes high, and parasitic capacitance between the first wiring and the second wiring increases. In addition, as shown i
Flynn Nathan J.
Mondt Johannes P.
NEC Electronics Corporation
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