Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-04-04
1999-02-23
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711146, 711163, 711169, 711158, 711145, G06F 1208, G06F 1318
Patent
active
058754679
ABSTRACT:
A method of maintaining cache coherency for snoop operations includes initiating a first snoop operation in response to a snoop request while one or more previous snoop operations are pending in a queue. Furthermore, one or more subsequent snoop operations can be queued, wherein a step of determining if the one or more snoop requests are orthogonal, i.e. the processing of one request is not dependent on the outcome of a previous request, is included. The step of determining if the one or more snoop requests are orthogonal includes utilizing a block bit, a sleep bit, and a plurality of previously pending snoop request bits in a snoop queue entry to determine if the entry is orthogonal or not.
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Bragdon Reginald G.
Intel Corporation
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