Semiconductor memory device with bit lines having reduced...

Details Semiconductor memory device with bit lines having reduced... Semiconductor memory device with bit lines having reduced...

2000-07-28

2003-11-11

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S211000

Reexamination Certificate

active

06646312

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, such as a mask ROM (Read-Only Memory) and a method for fabricating the same.
BACKGROUND OF THE INVENTION
As a higher degree of integration is realized for LSIs, parasitic capacitance between two adjacent conductive lines is remarkably increased; and therefore a cross-talk noise is increased in LSIs. Such a cross-talk noise is critical to a memory device, such as a ROM (Read-Only Memory).
A ROM stores a large amount of data, which are read out when necessary. There is a demand for a higher degree of integration to such a ROM. In a ROM, each memory cell block includes memory cells arrayed in a matrix configuration. Each memory cell is constituted by MOS transistors. These MOS transistors are connected at gate electrodes to word lines, which are extended in a first direction. One of the source or drain regions of the MOS transistors are connected to bit lines, which are extended in a second direction orthogonal to the first direction.
When parasitic capacitance between adjacent two bit lines is increased, an operation error may be made due to a cross-talk noise.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor memory device that contributes to reduce affection of a cross-talk noise due to parasitic capacitance between adjacent two bit lines.
Another object of the present invention is to provide a method for fabricating a semiconductor memory device that contributes to reduce affection of a cross-talk noise due to parasitic capacitance between adjacent two bit lines.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor memory device is fabricated to have a multi-layered structure on a semiconductor substrate. The semiconductor memory device includes ground lines, which are formed in a first conductive layer; bit lines, which are formed in a second conductive layer; and word lines, which are formed in a third conductive layer. The bit lines are not formed in the uppermost conductive layer.
According to a second aspect of the present invention, a semiconductor memory device is fabricated to have a multi-layered structure on a semiconductor substrate. In the method, a first conductive layer for ground lines is provided; a second conductive layer for bit lines is provided; and a third conductive layer for word lines is provided. The bit lines are not provided in the uppermost conductive layer.


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Wolf, “Silicon Processing for the VLSI Era, vol. 2—Process Integration,” 1990, Lattice Press, p. 194-196.*
Wolf, “Silicon Processing for the VLSI Era, vol. 2—Process Integration,” 1990, Lattice Press, p. 274.*
Wolf, “Silicon Processing for the VLSI Era, vol. 2—Process Integration,” 1990, Lattice Press, p. 191 and 273.

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