Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-05-11
2003-10-14
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S305000, C257S306000, C257S336000, C257S339000, C257S342000, C257S344000, C257S345000, C257S409000
Reexamination Certificate
active
06633059
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly relates to a method for manufacturing an integrated circuit (IC) a or other such semiconductor device having a MOS transistor.
b) Description of the Related Art
The use of a salicide (self-aligned silicide) process is a known method for manufacturing a MOS transistor with an LDD (Lightly Doped Drain) structure having low-resistance source and drain regions. With this method, the size of the source and drain regions has to be increased in circuit areas that require high resistance, such as input/output protection circuits, and this was disadvantageous in terms of raising the integration of the transistor.
In view of this, methods that improve on the salicide process have been proposed for manufacturing a MOS transistor with an LDD structure having high-resistance source and drain regions (see JP-A-Hei 5-3173, for example).
FIGS. 21
to
23
illustrate the steps for manufacturing a MOS transistor having high-resistance source and drain regions and a MOS transistor having low-resistance source and drain regions according to this method.
In the step in
FIG. 21
, a field insulation film
11
having element holes
11
a
and
11
b
is formed on the surface of a p type silicon substrate
10
, after which gate insulation films
12
a
and
12
b
are formed on the surface of the silicon substrate
10
inside the element holes
11
a
and
11
b
. A poly-Si (silicon) layer and a WSi (tungsten silicide) layer are deposited successively on the substrate surface, after which the poly-Si and WSi layers are patterned in the desired gate pattern to form gate electrode layers Ga and Gb over the gate insulation films
12
a
and
12
b
, respectively. The gate electrode layer Ga comprises the poly-Si layer
13
a
and WSi layer
14
a
remaining after the patterning, and the gate electrode layer Gb comprises the poly-Si layer
13
b
and WSi layer
14
b
remaining after the patterning.
Next, the surface of the silicon substrate
10
inside the element holes
11
a
and
11
b
is selectively doped with n-type impurities using the gate insulation film
12
a
and the gate electrode layer Ga, the gate insulation film
12
b
and the gate electrode layer Gb, and the field insulation film
11
as masks, which forms an n-type source region
15
s
and drain region
15
d
, and forms an n-type source region
16
s
and drain region
16
d
. A silicon oxide film is deposited on the substrate surface as a side spacer material film, after which this side spacer material film is etched to form side spacers
17
s
and
17
d
on both side walls of the gate electrode layer Ga, and to form side spacers
18
s
and
18
d
on both side walls of the gate electrode layer Gb. The etching treatment here results in the etching of the portions of the gate insulation films
12
a
and
12
b
not covered by the gate electrode layers Ga and Gb and the side spacers
17
s
,
17
d
,
18
s
, and
18
d
, and in the exposure of the source regions
15
s
and
16
s
and drain regions
15
d
and
16
d.
Next, a silicon oxide film is deposited on the substrate surface as an anti-silicide conversion film, after which the anti-silicide conversion film is etched using a resist layer as a mask, which leaves behind an anti-silicide conversion film
19
that covers a first gate component including the gate insulation film
12
a
, the gate electrode layer Ga, and the side spacers
17
s
and
17
d
; a portion Rs of the source region
15
s
that is adjacent to the first gate component; and a portion Rd of the drain region
15
d
that is adjacent to the first gate component. After this, a Ti (titanium) film
20
is deposited as a silicide-forming metal film on the substrate surface.
In the step in
FIG. 22
, after a silicide conversion treatment has been performed, the unreacted portion of the Ti film
20
is removed by etching. As a result, silicide layers
21
s
,
21
d
,
22
s
, and
22
d
are formed in the source region
15
s
, the drain region
15
d
, source region
16
s
, and the drain region
16
d
, respectively. No silicide conversion reaction occurs in the WSi layer
14
b
of the gate electrode layer Gb at this point.
In the step in
FIG. 23
, the anti-silicide conversion film
19
is removed by etching. The surface of the silicon substrate
10
inside the element holes
11
a
and
11
b
is selectively doped with n type impurities via the silicide layers
21
s
,
21
d
,
22
s
, and
22
d
and using a first gate component including the gate insulation film
12
a
, the gate electrode layer Ga, and the side spacers
17
s
and
17
d
; and a second gate component including the gate insulation film
12
b
, the gate electrode layer Gb, and the side spacers
18
s
and
18
d
; and the field insulation film
11
as masks, which forms an n
+
type source region
23
s
and drain region
23
d
, and forms an n
+
type source region
24
s
and drain region
24
d.
With the above manufacturing method, as to the MOS transistor formed inside the element hole
11
a
, no silicide layer is formed on the portion Rs of the source region
23
s
directly covered by the anti-silicide conversion film
19
, or on the portion Rd of the drain region
23
d
directly covered by the anti-silicide conversion film
19
, and both of these portions Rs and Rd are high-resistance components. Meanwhile, as to the MOS transistor formed inside the element hole
11
b
, since no anti-silicide conversion film such as the film
19
was positioned in either the source region
24
s
or the drain region
24
d
, the silicide layers
22
s
and
22
d
account for the majority of the source region
24
s
and the drain region
24
d
, which means that the source region
24
s
and the drain region
24
d
are both low in resistance.
The MOS transistor inside the element hole
11
a
has high resistance to electrostatic discharge (ESD), and is used for an IC input/output circuit or the like. The MOS transistor inside the element hole
11
b
, meanwhile, has low resistance to ESD, and is used for an IC internal circuit or the like. With the above manufacturing method, the location where the anti-silicide conversion film
19
is formed may be somewhat out of position due to misalignment during the formation of the resist layer that serves as the etching mask by photolithography. A problem with this is the large amount of variance in the resistance values of the high- and low-resistance components Rs and Rd.
Also, three more steps are required than in an ordinary salicide process, namely, the deposition, patterning, and removal of the anti-silicide conversion film, which is a problem in terms of a greater number of manufacturing steps.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for manufacturing a semiconductor device, with which a MOS transistor with high ESD resistance can be manufactured at a good yield.
According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of:
(a) providing a substrate having a first silicon region;
(b) forming a gate electrode layer on said first silicon region so that it is divided into a source disposition component and a drain disposition component;
(c) forming an insulating first mask layer in said source disposition component so that said source disposition component is divided into a first source disposition component and a second source disposition component, and forming an insulating second mask layer in said drain disposition component so that said drain disposition component is divided into a first drain disposition component and a second drain disposition component; and
(d) forming a silicide layer over said first and second source disposition components and in said first silicon region located in said first and second drain disposition components, using said first and second mask layers as a mask.
According to another aspect of the present invention, there is provided a method for man
Wojciechowicz Edward
Yamaha Corporation
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