Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-01
2003-02-25
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S592000, C438S594000, C438S618000, C438S637000, C438S647000, C438S657000
Reexamination Certificate
active
06524951
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming silicide interconnects over silicon comprising substrates, and to methods of forming stacks of refractory metal nitrides over refractory metal suicides over silicon.
BACKGROUND OF THE INVENTION
In the processing of integrated circuits, electrical contact is typically made to isolated active device regions formed within a wafer substrate typically comprising monocrystalline silicon. The active regions are typically connected by electrically conductive paths or lines which are fabricated above an insulative material formed over the substrate surface. Further, electrical contact is also typically made to other conductive regions received outwardly of the wafer, such as to conductive lines, contact plugs and other devices. To provide electrical connection between two conductive regions, an opening in an insulative layer is typically etched to the desired regions to enable subsequently formed conductive films to make electrical connection with such regions.
The drive for integrated circuits of greater complexity, performance and reduced size has driven designers to shrink the size of devices in the horizontal plane. Yet to avoid excessive current density, the horizontal scaling has not necessarily been accompanied by a reduction in the vertical dimension. This has resulted in an increase of the ratio of device height to device width, something generally referred to as aspect ratio, and particularly with respect to contact openings. Such currently ranges from 1.0 to 5, and is expected to increase. The circuit density increase places increasing constraints on the conductivity of the contacts themselves.
As transistor active area and other device dimensions approached 1 micron, conventional process parameters resulted in intolerable increased resistance between the active region or device area and the conductive layer. A principal way of reducing such contact resistance is by formation of a metal silicide atop the active area prior to application of the conductive film for formation of the conductive runner. Common metal suicides are refractory metal silicides, such as TiSi
x
, where “x” is predominately 2. The TiSi
x
material is typically provided by first applying a thin layer of titanium atop the wafer which contacts the silicon containing active areas within the contact openings. Thereafter, the wafer is subjected to a high temperature anneal. This causes the titanium to react with the silicon of the active area, thus forming the TiSi
x
. Such a process is said to be self-aligning, as the TiSi
x
is only formed where the titanium metal contacts silicon. The applied titanium film typically everywhere else overlies an insulative, and substantially non-reactive, SiO
2
layer. After the first annealing, unreacted titanium may be removed selectively relative to the formed silicide by a wet etch. Further, a post-silicidation anneal might be conducted to lower sheet resistance of the formed silicide.
In the silicidation process, silicon from contact regions of the substrate diffuses upward into the refractory metal layer. Similarly, the refractory metal diffuses into the underlying silicon. The intent is for the titanium and silicon to react with each other to form a silicide thick enough to provide low sheet resistance and make a highly conductive contact interface. As a result, the doped active area of the silicon substrate (or other silicon construction) becomes thinner due to the consumption of silicon during the reaction. The resultant silicide is said to intrude or sink into the substrate or device. Over-consumption of the underlying silicon can be problematic for any silicon circuit element, tending to cause voids and thus device failures. Tendency in the industry is to make shallower and shallower active area junctions in the silicon substrates. In some instances, silicide contacts of sufficient thickness cannot be formed without completely destroying a junction because of silicon consumption from the underlying substrate.
The invention was principally motivated in addressing these problems, but is not so limited and has other applicabilities as will be appreciated by the artisan.
SUMMARY
The invention encompasses methods of forming silicide interconnects over silicon comprising substrates. In one implementation, a first layer comprising a metal and a non-metal impurity is formed over a region of a silicon comprising substrate where a silicide interconnection is desired. An elemental metal comprising second layer is formed over the first layer. The substrate is annealed to cause a reaction between at least the elemental metal of the second layer and silicon of the substrate region to form a silicide of the elemental metal of the second layer.
In another considered aspect, a method of forming a silicide interconnect over a silicon comprising substrate includes providing a buffering layer to silicon diffusion between a refractory metal comprising layer and a silicon containing region of a substrate. The substrate is annealed under conditions effective to diffuse at least some of at least one of the refractory metal and the silicon through the buffering layer to form a silicide of the refractory metal, with the buffering layer during the annealing reducing silicon consumption from the region over that which would otherwise occur under the same annealing conditions were the buffering layer not present.
In another considered aspect, a method of forming a stack of refractory metal nitride over refractory metal silicide over silicon includes providing a silicon comprising substrate. A first layer comprising MN
x
is formed over the silicon comprising substrate, where M is a refractory metal and “x” is greater than 0 and less than 1. A second layer predominately comprising elemental M is formed over the first layer. The substrate is annealed in a nitrogen containing atmosphere to cause a reaction of at least M of the first layer with silicon of the substrate to form a silicide of M in contact with underlying silicon material of the substrate and react M of the second layer to transform a least an outermost portion of the second layer to predominately comprise a stoichiometric nitride of M.
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Nelms David
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