Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-28
2003-11-04
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S318000, C257S320000
Reexamination Certificate
active
06642568
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device to be produced through the utilization of STI technique which is designed such that a gate insulation film and a gate electrode are successively formed at first and then a device isolating insulation film is buried, and also to a manufacturing method which is applicable to the manufacture of such a semiconductor device.
The STI (Shallow Trench Isolation) technique has been conventionally known as a device isolating technique which is adapted to be employed in the manufacture of a high-integrated memory such as an NAND type EEPROM, etc. This technique is featured in that a shallow trench is formed as a device isolating region on the surface of semiconductor substrate, and then, a device isolating insulation film is buried or filled in this groove. In the specific application of this STI technique, it is possible to utilize either [a] a system wherein a device isolating insulation film is buried in a groove at first, and then, a gate insulation film and a gate electrode are successively formed in a device region; or [b] a system wherein a gate insulation film and a gate electrode material film are successively formed all over the surface of substrate at first, and then, these gate electrode material film and gate insulation film as well as the surface of substrate are selectively etched away to form a groove, into which a device isolating insulation film is subsequently filled.
FIGS. 1A
,
1
B, and
2
A to
2
C schematically show one example of the conventional manufacturing process of the NAND type EEPROM, wherein the aforementioned system [b] is utilized. Specifically,
FIG. 1A
shows a plan view schematically illustrating one of the manufacturing steps; and
FIG. 1B
shows a cross-sectional view taken along the line
1
B—
1
B of the structure shown in FIG.
1
A. On the other hand,
FIG. 2A
shows a plan view schematically illustrating a post step subsequent to the step shown in
FIGS. 1A and 1B
;
FIG. 2B
shows a cross-sectional view taken along the line
2
B—
2
B of the structure shown in
FIG. 2A
; and
FIG. 2C
shows a cross-sectional view taken along the line
2
C—
2
C of the structure shown in FIG.
2
A. By the way, in these
FIGS. 1A
,
1
B, and
2
A to
2
C, the reference numeral
2
denotes a device region, and the reference numeral
4
denotes a device isolating insulation film defining the device isolating region.
According to the conventional manufacturing process of the NAND type EEPROM, wherein the aforementioned system [b] is utilized, a gate insulation film (tunnel insulation film)
5
, a gate electrode material film
6
a
to be formed into a portion of a floating gate electrode, and a silicon nitride film
7
to be employed as a stopper film in a CMP (Chemical Mechanical Polishing) treatment are successively formed at first on the surface of a silicon substrate
1
. Then, by making use of a resist pattern as a mask, the gate electrode material film
6
a
, the gate insulation film
5
and the surface of silicon substrate
1
are selectively etched away by means of RIE method, thereby forming a groove
3
. Thereafter, the device isolating insulation film
4
is formed so as to fill the groove
3
with the device isolating insulation film
4
, and the redundant portion of the device isolating insulation film
4
which is located outside the groove
3
is removed by means of CMP method, thereby obtaining the structure shown in
FIGS. 1A and 1B
.
Next, the silicon nitride film
7
is removed, and a regressing treatment to remove an upper portion of the device isolating insulation film
4
which protrudes from the groove
3
is performed. Then, a gate electrode material film
6
b
to be employed as a floating gate electrode
6
in combination with the gate electrode material film
6
a
is formed. After a slit is formed in each of the portions of the gate electrode material film
6
b
which are located respectively over the device isolating insulation film
4
, an interlayer gate insulation film
8
is formed all over the gate electrode material film
6
b
including the slit portions. Then, a control gate electrode film
9
is formed on the surface of this interlayer gate insulation film
8
. Subsequently, the control gate electrode film
9
, the interlayer gate insulation film
8
, the gate electrode material film
6
b
and the gate electrode material film
6
a
are patterned en bloc to obtain a structure as shown in
FIGS. 2A
to
2
C.
In the structure shown in
FIGS. 2A
to
2
C, the floating gate electrodes
6
adjacent to each other in the arraying direction of the control gate electrode
9
are required to be insulated from each other. However, according to the aforementioned method, since the upper portion of the device isolating insulation film
4
that protrudes from the groove
3
is reverse tapered in cross-section, a peripheral portion of the gate electrode material film
6
a
is caused to be located below the side surface of the device isolating insulation film
4
. As a result, as shown in
FIG. 2C
, this peripheral portion of the gate electrode material film
6
a
which is located below the side surface of the device isolating insulation film
4
is failed to be etched and caused to be left remained thereat on the occasion of the patterning process of the gate electrode material film
6
a
. Namely, an etching residue
10
is caused to be produced between the control gate electrode
9
adjacent to each other. This etching residue
10
naturally invites the short circuit between adjacent floating gate electrodes
6
located in the arraying direction of the control gate electrode
9
. Namely, the conventional manufacturing process of the NAND type EEPROM where the aforementioned system [b] is utilized is accompanied with the problem that the short circuit between floating gate electrodes is likely to be occurred.
BRIEF SUMMARY OF THE INVENTION
The present invention has been achieved in view of the aforementioned problem, and therefore, an object of the present invention is to provide an STI technique wherein a gate insulation film and a gate electrode material film are successively formed at first and then, a device isolating film is buried, and which is improved so as to prevent the short circuit between the gate electrodes.
Another object of the present invention is to provide a semiconductor device and a manufacturing method of the semiconductor device, which are featured in that the occurrence of short circuit between gate electrodes can be substantially suppressed in the manufacturing process of semiconductor device.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a transistor comprising a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film comprising a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising forming a laminate structure comprising a gate insulation film on a semiconductor substrate and a gate electrode material film on the gate insulation film, processing the gate electrode material film to obtain a gate electrode having a reverse tapered cross section, and forming a device isolating insulation film being in direct contact with a side surface of the gate electrode.
By the term “forward tapered”, it is meant that as far as it is employed with reference to a recessed portion s
Kobayashi Hideyuki
Narita Kazuhito
Sakagami Eiji
Sonoda Masahisa
Tsunoda Hiroaki
Kabushiki Kaisha Toshiba
Rose Kiesha
Zarabian Amir
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3154277