Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-10-05
2003-02-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189011, C365S230010
Reexamination Certificate
active
06515920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor data storing circuit device, a method of checking the semiconductor data storing circuit device and a method of relieving the semiconductor data storing circuit device from a defective cell.
2. Description of Related Art
FIG. 19
is a block diagram showing the configuration of a system LSI in which a plurality of static random access memory (SRAM) cores are arranged. The system LSI denotes an example of a conventional semiconductor data storing circuit device. In
FIG. 19
,
101
indicates a semiconductor chip,
102
indicates each of a plurality of pads,
103
indicates each of a plurality of memory cores (SRAM cores),
104
indicates each of a plurality of logical circuits, and
105
indicates each of a plurality of selecting circuits. Each selecting circuit
105
selects either one logical circuit
104
or a terminal
202
to be used for a test operation.
FIG. 20
is a block diagram showing the configuration of each memory core
103
shown in FIG.
19
. In
FIG. 20
,
106
indicates a memory cell array having 8×16 memory cells arranged in 8 rows and 16 columns.
106
a
indicates each of 128 (8×16) memory cells (hereinafter, called cells).
106
b
indicates each of 16 bit lines.
106
c
indicates each of 8 word lines.
107
indicates a row decoder.
108
indicates each of a plurality of precharge circuits.
109
indicates a column decoder.
110
indicates another column decoder.
111
indicates each of eight multiplexers of one-input (or one-output) and two-output (or two-input). The multiplexer
111
is arranged at every two columns.
112
indicates each of four demultiplexers of one-input and two-output. The demultiplexer
112
is arranged at every four columns.
113
indicates each of four multiplexers of two-input and one-output. The multiplexer
113
is arranged at every four columns.
114
indicates eight sense amplifiers respectively arranged at every two columns.
115
indicates eight write drivers respectively arranged at every two columns.
116
indicates each of four input buffers respectively arranged at every four columns.
117
indicates each of four output buffers respectively arranged at every four columns. D
0
, D
1
, D
2
and D
3
indicate four data input pins. Each data input pin is arranged at every four columns. Q
0
, Q
1
, Q
2
and Q
3
indicate four data output pins. Each data output pin is arranged at every four columns.
Therefore, the memory cell array
106
has a cell configuration of 8 rows and 16 columns. Also, because each bit of the input/output data corresponds to four columns, the memory cell array
106
has a cell configuration of 32 words and 4 bits.
Next, an operation of the memory core
103
will be described below.
A plurality of specific rows are specified by a row address signal input to the row decoder
107
, and a plurality of specific columns are specified according to a column address signal input to the column decoders
109
and
110
. Thereafter, in a write mode operation, four bits of data input to the corresponding data input pins D
0
, D
1
, D
2
and D
3
are written in four specific cells arranged in the specific rows and the specific columns respectively through the corresponding input buffers
116
, the corresponding demultiplexers
112
, the corresponding write drivers
115
and the corresponding multiplexers
111
. In contrast, in a read mode operation, four bits of data stored in four specific cells of the specific rows and the specific columns are read out as four bits of test data to the corresponding data output pins Q
0
, Q
1
, Q
2
and Q
3
through the corresponding multiplexers
111
, the corresponding sense amplifiers
114
, the corresponding multiplexers
113
and the corresponding output buffers
117
, and the bits of test data are output from the corresponding data output pins Q
0
, Q
1
, Q
2
and Q
3
.
FIG. 21
is a block diagram showing the configuration of each memory core
103
in which a checking circuit is arranged. In
FIG. 21
,
118
indicates each of 4 multiplexers of two-input and one-output. The multiplexer
118
is arranged at every four columns.
119
indicates each of four demultiplexers of one-input and two-output. The demultiplexer
119
is arranged at every four columns.
120
indicates a controller.
121
a
indicates a column address selector.
121
b
indicates another column address selector.
122
indicates a row address selector. TD
0
, TD
1
, TD
2
and TD
3
indicate four test data input pins. TQ
0
, TQ
1
, TQ
2
and TQ
3
indicate four test data output pins. The other constituent elements, which are the same as those shown in
FIG. 20
, are indicated by the same reference numerals as those shown in FIG.
20
.
Next, an operation of the memory core
103
shown in
FIG. 21
will be described below.
In cases where an operation mode changing signal input to the controller
120
indicates a normal operation mode, each multiplexer
118
is connected with the corresponding data input pin D
0
, D
1
, D
2
or D
3
, each of the column address selectors
121
a
and
121
b
selects a column address signal, and the row address selector
122
selects a row address signal. Therefore, the same operation as that performed in the memory core
103
shown in
FIG. 20
is performed in each of the write and read modes.
In contrast, in cases where an operation mode changing signal input to the controller
120
indicates a test operation mode, each multiplexer
118
is connected with the corresponding test data input pin TD
0
, TD
1
, TD
2
or TD
3
, each of the column address selectors
121
a
and
121
b
selects a test column address signal, and the row address selector
122
selects a test row address signal.
In this case, a plurality of specific rows are specified according to a test row address signal input to the row decoder
107
, and a plurality of specific columns are specified by a test column address signal input to the column decoders
109
and
110
. Thereafter, in a write mode operation, four bits of data input to the test data input pins TD
0
, TD
1
, TD
2
and TD
3
are written in four specific cells of the specific rows and the specific columns through the corresponding input buffers
116
, the corresponding multiplexers
118
, the corresponding demultiplexers
112
, the corresponding write drivers
115
and the corresponding multiplexers
111
. In contrast, in a read mode operation, four bits of data stored in four specific cells of the specific rows and the specific columns are read out from the corresponding test data output pins TQ
0
, TQ
1
, TQ
2
and TQ
3
through the corresponding multiplexers
111
, the corresponding sense amplifiers
114
, the corresponding multiplexers
113
, the corresponding demultiplexers
119
and the corresponding output buffers
117
.
Therefore, in cases where the test operation mode is performed in each memory core
103
shown in
FIG. 21
, the memory cell array
106
has a cell configuration of 16 columns×8 rows in the same manner as that in the normal operation mode. Also, because each bit of the input/output test data corresponds to four columns, the memory cell array
106
has a cell configuration of 32 words×4 bits. Therefore, an operation check for each memory core
103
is performed according to a checking program applied to a cell configuration of 32 words×4 bits in the manufacturing of the system LSI.
Because the semiconductor data storing circuit device (or the system LSI) arranged on a semiconductor chip has the above configuration, in cases where a large number of input/output pins are arranged in the device, a problem has arisen that it is difficult to arrange a plurality of test input/output pins corresponding to the input/output pins.
Also, in cases where a large number of columns correspond to each bit of data input or output in the normal operation mode, another problem has arisen that a test operation time is lengthened so as to increase a manufacturing cost of the device.
Also, in cases where word-bit configuratio
Miyanishi Atsushi
Morizane Sizuo
Nakano Hirofumi
Auduong Gere N.
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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