High density read only memory cell configuration and method for

Details High density read only memory cell configuration and method for High density read only memory cell configuration and method for

1997-02-03

1998-10-13

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257329, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

058215913

ABSTRACT:
A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F.sup.2, where F is the minimum structure size.

REFERENCES:
patent: 4914740 (1990-04-01), Kenney
patent: 4954854 (1990-09-01), Dhong et al.
patent: 5306941 (1994-04-01), Yoshida
patent: 5670803 (1997-09-01), Beilstein et al.
Patent Abstracts of Japan No. 03190165 (Ikuo), dated Aug. 20, 1991.
Patent Abstracts of Japan No. 07142610 (Taira), dated Jun. 2, 1995.
Patent Abstracts of Japan No. 02106966 (Noboru), dated Apr. 19, 1990.

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