Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-08
2003-12-02
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S317000, C257S318000, C438S201000, C438S211000, C438S257000
Reexamination Certificate
active
06657249
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more specifically, it relates to a nonvolatile semiconductor memory device capable of readily distinctively forming a transistor in a memory cell part and transistors in a peripheral circuit part while reducing the number of times of high-temperature heat treatment.
2. Description of the Background Art
Referring to
FIG. 34
, a conventional nonvolatile semiconductor memory device is divided into a memory cell part R
1
and a peripheral circuit part R
2
located in the periphery thereof. A memory cell transistor
150
is arranged on the memory cell part R
1
while two types of transistors
161
and
162
are arranged on the peripheral circuit part R
2
. The difference between the two types of transistors
161
and
162
resides in difference between the thicknesses of gate insulator films
127
and
137
, as described later.
FIG. 34
shows the memory transistor
150
of the memory cell part R
1
in two sections along bit and word lines respectively. An n-conductivity type bottom well
103
is provided at a part of the bottom of a silicon substrate
101
formed in the memory cell part R
1
isolated from the peripheral circuit part R
2
by an element isolation zone
102
. A p-conductivity type well
105
is formed at the n-conductivity type bottom well
103
. The memory cell transistor
150
has source and drain regions
108
a
and
180
b
formed in the p-conductivity type well
105
and a gate insulator film
106
arranged on the silicon substrate
101
. A floating gate
107
enclosed with an insulating region
109
is arranged on the gate insulator film
106
. An inter-gate isolation film
110
consisting of a three-layer insulator film including a silicon oxide film, a silicon nitride film and a silicon oxide film is formed on the floating gate
107
. A control gate
113
is arranged on the inter-gate isolation film
110
. A layer
114
of WSi and an insulator film
115
are arranged on the control gate
113
.
An n-conductivity type well
104
and a p-conductivity type well
105
are provided on the peripheral circuit part R
2
. The two types of transistors
161
and
162
are provided in each of the wells
104
and
105
. The transistor
161
has a gate oxide film
127
, and the transistor
162
has a gate oxide film
137
having a larger thickness than the gate oxide film
127
. Conductive layers
113
of the same perpendicular structure as the control gate
113
, WSi films
114
and insulator films
115
are provided on the gate oxide films
127
and
137
respectively. In the peripheral circuit part R
2
, the transistors
161
and
162
include low-concentration impurity regions
116
and
117
provided on the silicon substrate
101
and high-concentration impurity regions
119
and
120
formed by implanting an impurity through masks defined by side wall spacers provided on the side surfaces of gate electrodes. Plug wires
125
conductive with wires
126
arranged on an interlayer dielectric film
124
are connected to the high-concentration impurity regions
119
and
120
.
A method of fabricating the conventional nonvolatile semiconductor memory device is now described with reference to
FIGS. 35
to
43
.
First, the element isolation zone
102
is formed on the main surface of the p-conductivity type silicon substrate
101
having <100>crystal orientation (see FIG.
35
). Then, a resist pattern is formed on the main surface of the silicon substrate
101
as a mask for ion-implanting phosphorus into the memory cell part R
1
with acceleration energy of 3 MeV and density of 1.0E13, for example, thereby forming the n-conductivity type bottom well region
103
, and the resist pattern is removed. In the following description, processing of removing a resist film is not described.
Then, phosphorus is ion-implanted into the region of the peripheral circuit part R
2
to be formed with p-conductivity type MOS (metal oxide semiconductor) transistors with acceleration energy of 1.2 MeV and density of 1.0E13, for example, through a resist pattern serving as a mask. Further, phosphorus for channel cutting and boron for counter doping are ion-implanted into the same region with 700 keV and 3.0 E 12 and with 20keV and 1.5 E12 respectively, for example. The n-conductivity type well region
104
is formed by this ion implantation (see FIG.
35
).
Then, the p-conductivity type well regions
105
are formed in the region of the peripheral circuit part R
2
to be formed with n-conductivity type MOS transistors and a region of the memory cell part R
2
to be formed with a memory cell through a resist pattern serving as a mask in the following three stages (a), (b) and (c) (see FIG.
35
): (a) Boron is ion-implanted with acceleration energy of 700 keV and density of about 1.0E13, for example. (b) Boron for p-channel cutting is ion-implanted with acceleration energy of 270 keV and density of 3.5E12, for example. (c) Boron for channel doping is ion-implanted with acceleration energy of 50 keV and density of 1.2E12, for example.
Thereafter a silicon oxide film
106
of about 10 nm in thickness is formed on the main surface of the silicon substrate
101
by thermal oxidation. Then, a phosphorus-doped polycrystalline silicon film
107
of about 200 nm in thickness is formed. Thereafter a resist pattern is formed on the overall main surface of the silicon substrate
101
by photolithography. This resist pattern is employed as a mask for patterning the phosphorus-doped polycrystalline silicon film
107
thereby forming the floating gate
107
on the region to be formed with the memory transistor
150
.
Then, arsenic is ion-implanted into the region of the silicon substrate
101
to be formed with the memory cell with acceleration energy of 35 keV and density of about 3.0E15, for example, through a resist pattern serving as a mask for forming n-conductivity type impurity diffusion regions as the source and drain regions
108
a
and
108
b
. Thereafter a silicon oxide film
109
of 800 nm in thickness is deposited on the silicon substrate
101
by low-pressure CVD (chemical vapor deposition). The overall surface of this silicon oxide film
109
is etched thereby exposing the surface of the phosphorus-doped polycrystalline silicon film
107
(see FIG.
35
).
Then, the three-layer insulator film
110
is formed on the main surface of the silicon substrate
101
. In formation of the three-layer insulator film
110
, a silicon oxide film of 5 nm in thickness is first formed by thermal oxidation. Then, a silicon nitride film of 10 nm in thickness is formed thereon by low-pressure CVD. Further, another silicon oxide film of 5 nm in thickness is formed thereon by low-pressure CVD, thereby defining the three-layer insulator film
110
.
Thereafter a resist pattern is formed on the silicon substrate
101
by photolithography. This resist pattern is employed for patterning the three-layer insulator film
110
, the phosphorus-doped polycrystalline silicon film
107
and the gate oxide film
106
on the peripheral circuit part R
2
, as shown in FIG.
35
.
Thereafter silicon oxide films
111
of about 20 nm in thickness are formed on the regions of the peripheral circuit part R
2
to be formed with thick gate insulator films, i.e., to be formed with high withstand voltage transistors. At this time, the silicon nitride film included in the three-layer insulator film
110
prevents the underlayer from thermal oxidation in the memory cell part Rd. Then, resist patterns are formed on the regions of the peripheral circuit part R
2
to be formed with the high withstand voltage transistors and the memory cell part R
1
by photolithography for patterning the silicon oxide films
111
in regions of the peripheral circuit part R
2
to be formed with low withstand voltage transistors (FIG.
36
).
A silicon oxide film
127
of about 10 nm for defining the gate oxide films of the low withstand voltage transistors of the peripheral circuit part R
2
is grown on the silicon substrate
101
Nishioka Naho
Tsuji Naoki
McDermott & Will & Emery
Tran Long
LandOfFree
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