Semiconductor device including inversely tapered gate...

Details Semiconductor device including inversely tapered gate... Semiconductor device including inversely tapered gate...

1999-09-22

2003-12-09

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S344000, C257S365000, C257S366000, C257S413000

Reexamination Certificate

active

06661066

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof, and particularly to an MOSFET having a gate electrode formed of metal film and a manufacturing method thereof.
2. Description of the Background Art
Polycide gates having stacked structure of polysilicon film and metal silicide film are widely used as the gate electrodes of MOSFETs. However, formation of the gate electrodes with metal film, such as tungsten film, is effective to reduce the gate resistance so as to realize higher-speed operation of the MOSFETs.
When a gate electrode is formed of metal film, heat treatment after the formation of the gate electrode is restricted because of the low thermal resistance of the metal film and some other reasons. For example, the heat treatment to the source/drain regions which are usually formed after the formation of the gate electrode is restricted and the dopant is insufficiently activated, and then the source/drain resistance is increased to lower the driving capability of the MOSFET. To solve this inconvenience, a method of forming the source/drain regions before formation of the gate electrode is suggested, in which a dummy electrode is formed for the gate electrode (the replace method).
FIG. 36
is a sectional view showing the structure of an MOSFET having a gate electrode formed by a conventional replace method (Ext. Abst. of International Electron Devices Meeting 1998, pp.785-788). The conventional MOSFET shown in
FIG. 36
has a semiconductor substrate
101
, a trench-type element isolation structure
102
formed in the element isolation region in the main surface of the semiconductor substrate
101
, a pair of source/drain regions
103
selectively formed in the element formation region in the main surface of the semiconductor substrate
101
to face each other through the channel region, a silicon oxide film
104
formed on the trench-type element isolation structure
102
and on the source/drain regions
103
through a silicon oxide film
108
, a gate insulating film
105
formed on the main surface of the semiconductor substrate
101
in the part in which the silicon oxide film
104
is not formed in the element formation region, and a gate electrode
106
formed to fill the recessed portion formed by sides of the silicon oxide film
104
and the upper surface of the gate insulating film
105
.
FIGS. 37
to
42
are sectional views showing a method for manufacturing the MOSFET shown in
FIG. 36
in the order of process steps. First, the trench-type element isolation structure
102
filled with insulating film is formed in the element isolation region in the main surface of the semiconductor substrate
101
which is composed of single crystal silicon. Next, to form a well and to adjust the operation threshold voltage of the MOSFET, boron ions
107
are implanted into the semiconductor substrate
101
by an ion implantation (FIG.
37
).
Next, the silicon oxide film
108
is formed by a thermal oxidation on the main surface of the semiconductor substrate
101
. Subsequently, a polysilicon film and a silicon nitride film are formed in this order by CVD on the silicon oxide film
108
. After this, the polysilicon film and the silicon nitride film are patterned into given shape by photolithography and anisotropic dry etching to selectively form a dummy electrode
150
on the silicon oxide film
108
; the dummy electrode
150
has a stacked structure in which the polysilicon film
109
and the silicon nitride film
110
are stacked in this order (FIG.
38
).
Next, arsenic ions
111
are implanted into the semiconductor substrate
101
by an ion implantation to form the source/drain regions
103
in the main surface of the semiconductor substrate
101
(FIG.
39
). Subsequently, a thermal treatment is performed to activate the implanted arsenic ions
111
. Next, a silicon oxide film is formed on the entire surface by a CVD. After that, the silicon oxide film is polished by CMP (Chemical Mechanical Polishing) until the upper surface of the dummy electrode
150
is exposed to form the silicon oxide film
104
(FIG.
40
). Next, the dummy electrode
150
and the silicon oxide film
108
under the dummy electrode
150
are removed (FIG.
41
). In
FIG. 41
, the silicon oxide films
104
and
108
serve as a mold for forming the gate electrode.
Next, the gate insulating film
105
composed of silicon oxide film is formed on the main surface of the semiconductor substrate
101
by a thermal oxidation. Subsequently, a tungsten film
113
is formed all over the surface by CVD or sputtering (FIG.
42
). Next, by the CMP method, the tungsten film
113
is polished until the upper surface of the silicon oxide film
104
is exposed, thus providing the structure shown in FIG.
36
.
FIG. 43
is a sectional view showing the structure of another MOSFET having a gate electrode formed by a conventional replace method. (Ext. Abst. of International Electron Devices Meeting 1998, pp.777-780). The conventional MOSFET shown in
FIG. 43
has the semiconductor substrate
101
and the trench-type element isolation structure
102
which are the same as those in the MOSFET shown in
FIG. 36
, a pair of extensions
121
and source/drain regions
122
selectively formed in the element formation region in the main surface of the semiconductor substrate
101
to face each other with the channel region therebetween, a silicon oxide film
123
formed on the trench-type element isolation structure
102
and on the extensions
121
with a silicon oxide film
127
interposed therebetween, sidewalls
124
formed in sides of the silicon oxide film
123
, a gate insulating film
125
formed on the main surface of the semiconductor substrate
101
in the part in which the silicon oxide film
123
and the sidewalls
124
are not formed in the element formation region, and a gate electrode
126
formed to fill the recessed part formed by the sides of the sidewalls
124
and the upper surface of the gate insulating film
125
.
FIGS. 44
to
50
are sectional views showing a method of manufacturing the MOSFET shown in
FIG. 43
in the order of processes. First, by the same method as that described above, the same structure as that shown in
FIG. 37
is obtained. Subsequently, the silicon oxide film
127
is formed on the main surface of the semiconductor substrate
101
by a thermal oxidation. Next, by CVD, a polysilicon film is formed on the silicon oxide film
127
. Then, the polysilicon film is patterned into given shape by photolithography and anisotropic dry etching to selectively form a dummy electrode
128
composed of polysilicon film on the silicon oxide film
127
(FIG.
44
).
Next, arsenic ions
129
are implanted by an ion implantation into the semiconductor substrate
101
to form the extensions
121
in the main surface of the semiconductor substrate
101
(FIG.
45
). Next, a silicon nitride film is formed on the entire surface by a CVD. Subsequently, the silicon nitride film is etched by an anisotropic dry etching to form the sidewalls
124
composed of the silicon nitride film on the sides of the dummy electrode
128
. After that, arsenic ions
130
are implanted into the semiconductor substrate
101
by an ion implantation to form the source/drain regions
122
which are deeper than the extensions
121
(FIG.
46
). Then a thermal treatment is applied to activate the implanted arsenic ions
130
.
Next, a silicon oxide film is formed all over the surface by a CVD. Next, the silicon oxide film is polished by CMP until the upper surface of the dummy electrode
128
is exposed to form the silicon oxide film
123
(FIG.
47
). Next, the dummy electrode
128
and the silicon oxide film
127
under the dummy electrode
128
are removed (FIG.
48
). In
FIG. 48
, the silicon oxide films
123
and
127
and the sidewalls
124
serve as a mold for forming the gate electrode.
Next, the gate insulating film
125
composed of silicon oxide film is formed on the main surface of the semiconductor substrate
101
by a thermal oxi

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