Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-08-03
2003-11-18
Tran, Minh Lean (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S777000, C257S782000, C257S707000, C257S718000
Reexamination Certificate
active
06650006
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package having at least two chips disposed in a stacked manner therein.
BACKGROUND OF THE INVENTION
It is desired to develop a highly-integrated semiconductor chip with enhanced performance and functions used in electronic products. That is, more electronic components need to be integrated on a semiconductor chip of a certain dimension. However, such a semiconductor chip requires a high integration process in fabrication, which makes the fabricating cost increased, while the fabricating rate is not correspondingly improved.
In accordance with the abovementioned problem, U.S. Pat. Nos. 5,721,452, and 6,215,193 B1 disclose a semiconductor package, in which two chips are disposed on a chip carrier such as a substrate or a lead frame in a stacked manner, as shown in FIG.
1
. In such a conventional semiconductor chip
1
, a first chip
10
is mounted on a chip carrier
11
, and then two supporting elements
12
,
12
are attached to an upper surface
110
of the chip carrier
11
in a manner that the two supporting elements
12
,
12
are respectively spaced from side edges of the first chip
10
. Then, a second chip
13
is disposed on the first chip
10
in a perpendicularly stacked manner, while portions of the second chip
13
not contacting the first chip
10
are attached to the supporting elements
12
,
12
respectively for supporting. This makes bond pads
130
on the second chip
13
stably held, which is beneficial for bonding of bonding wires
14
.
However, problems described as follows have been found in the foregoing semiconductor package. First, the second chip
13
is attached to the first chip
10
through an adhesive layer
15
, while the adhesive layer
15
remains soft before carrying out a curing process. This therefore makes it difficult to control a top surface
150
of the adhesive layer
15
to be coplanarly positioned with a top surface
120
of the supporting element
12
. In such a case, problems are generated after the second chip
13
is attached to the adhesive layer
15
. For example, if the top surface
120
of the supporting element
12
is higher than the top surface
150
of the adhesive layer
15
, voids and accordingly a popcorn effect will be generated due to the incomplete attachment of the second chip
13
to the adhesive layer
15
. Further, if the top surface
120
of the supporting element
12
is lower than the top surface
50
of the adhesive layer
15
the portions of the second chips
13
not contacting the first chip
10
can not be adequately supported by the supporting elements
12
, making the second chip
13
possibly cracking and the bonding of the bonding wires
14
to the bond pads
13
on the second chip
13
deteriorated in a wire bonding process.
Moreover, coplanarity is hard to be achieved between the top surfaces
120
,
120
of the supporting elements
12
,
12
. In the condition of the top surfaces
120
,
120
being in different elevation, the second chip
13
attached to the top surface
120
,
120
will be slopingly positioned with respect to the upper surface
110
of the chip carrier
11
, which detrimentally affects the bonding quality of the bonding wires
14
.
Furthermore, during a molding process, the supporting elements
12
interposed between the second chip
13
and the chip carrier
11
will impede the flow of a molding resin, which tends to form voids in a gap between the second chip
13
and the chip carrier
11
, and subsequently generate a popcorn effect.
In addition, heat produced by the first chip
10
will be transmitted to the second chip
13
, while the heat increased in the second chip
13
can not be effectively dissipated making the second chip
13
undesirably affected in electrical performance.
Finally, in the semiconductor package
1
, since the first chip
10
and the second chip
13
are perpendicularly stacked with the supporting elements
12
supporting the second chip
13
, if a third chip is preferable to be disposed on the second chip
13
in a perpendicularly stacked manner, then neither forming supporting elements for supporting the third chip nor bonding of bonding wires can be successfully carried out, which restricts the semiconductor package
1
to accommodating two chips only.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a semiconductor package with stacked chips, in which the chips can be stacked in plenarily parallel on a chip carrier for assuring bonding quality of bonding wires. Further, the semiconductor package of the invention allows an upper chip to be firmly held without the need of supporting elements, while the upper chip can further be prevented from cracking in a wire bonding process, and voids can be prevented from forming in a molding resin used to fill a gap between the upper chip and the chip carrier in a molding process. Moreover, the invention allows the semiconductor package to accommodate at least two chips stacked therein as well as makes heat generated in the semiconductor package effectively dissipated.
In accordance with the above and other objectives, a semiconductor package with stacked chips is proposed in the present invention, including a chip carrier; at least one first chip attached to the chip carrier and electrically connected to the chip carrier, while the first chip has an active surface including an attachment area and at least one bond pad area adjacent to the attachment area; at least one second chip having an active surface and an inactive surface, while the active surface includes an attachment area for mounting at least one chip thereon, and at least one bond pad area adjacent to the attachment area for electrically connecting the second chip to the chip carrier, whereas on the inactive surface there is disposed a rigid interposer for mounting the second chip on the attachment area of the first chip with the rigid interposer interposed between the first chip and the second chip, and the bond pad area of the second chip disposed in a position not right above the first chip is sufficiently supported by the rigid interposer in a manner that the bond pad area of the first chip is exposed to outside of the second chip and the rigid interposer; and an encapsulant for encapsulating the first and second chips.
The rigid interposer can be made of a nonmetallic or metallic material in a predetermined thickness for having sufficient rigidity for supporting the second chip and preventing the second chip from cracking during a wire bonding process. Further, in order to effectively dissipate heat produced by the first chip and improve the heat dissipating efficiency of the semiconductor package, the rigid interposer is preferably made of a metallic material such as copper, aluminum, copper alloy and aluminum alloy. Moreover, the rigid interposer can be formed in surface area larger than that of the second chip for providing an enlarged heat dissipating area for the first and second chips, so as to farther enhance the heat dissipating efficiency. Furthermore, with the use of the rigid interposer for heat dissipation, on at least one side edge of the rigid interposer there can be formed an upwardly extending portion in a manner of not interfering with the exposure of the bond pad area of the first chip. The extending portion is used to increase the heat dissipating area, and further the extending portion can be formed with a lateral portion having a top surface thereof exposed to outside of the encapsulant, allowing heat to be transmitted from the first and second chips through the lateral portion of the rigid interposer for being dissipated to the atmosphere, so as to even further improve the heat dissipating efficiency
In addition, with no need of supporting elements for supporting the second chip on the chip carrier as previously depicted in the prior art, at least one third chip can be mounted on the attachment area of the second chip in a manner of not affecting the electrical connecting
Ho Tzong-Da
Hsiao Cheng-Hsu
Huang Chien-Ping
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
Tran Minh Lean
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