Logic power optimization algorithm

Details Logic power optimization algorithm Logic power optimization algorithm

1998-05-07

2003-12-02

Lintz, Paul R. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S019000

Reexamination Certificate

active

06658634

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to logic networks, and more particularly to a system and method for eliminating the unnecessary toggling of nodes in the logic network.
2. Related Art
Complimentary Metal Oxide Semiconductor (CMOS) technology is now universally applied in digital logic circuits. CMOS devices are fabricated to provide either a high or low output level (e.g., 0 or 5 volts) while drawing very little power from the power supply. Moreover, CMOS circuitry includes the advantage of nearly eliminating DC power. Nonetheless, as the size and complexity of CMOS integrated circuits continue to grow, a need still exists to eliminate the fairly large amount of AC power CMOS circuit designs consume.
In particular, considerable power is wasted in typical CMOS logic network designs because internal nodes toggle uselessly, calculating outputs which are frequently unneeded. In most current logic designs, the focus is on making sure the logic path is functionally correct for some required function in the machine cycle when the output is needed or latched for future use. Almost no focus is spent on paths that are not used in the current cycle. These “unused” paths, made up of many signals, are typically switching up and down until a steady state is reached, even though the output is not used. When the logic designer creates a new logic structure, the focus is on getting the correct output from each portion of the logic network only at the time when the particular output is needed. There is typically no focus on those outputs that are unneeded and unused. This thought process leads to many nodes within the network toggling when, in fact, they are doing no useful work. Thus, present design and synthesis methods for CMOS logic result in considerable wasted power because portions of the logic network are allowed to toggle even when the outputs from these portions are unneeded and unused.
Therefore, without some system of eliminating unnecessary toggling of gates in a CMOS circuit, digital logic designs will continue to consume unnecessarily high amounts of AC power.
SUMMARY OF THE INVENTION
Described herein is a system and method for modifying a digital logic network design to prevent the unnecessary toggling of nodes in the network. In particular, a simple design algorithm is provided to identify and control logic that is not needed during certain operations. The system may be implemented on a computer system in the form of a software program and comprises: a first program code mechanism for identifying and grouping all enabled latches, wherein each enabled latch includes a first input for receiving data from the network, and a second input for receiving a unique enable signal; a second program code mechanism for attaching an attribute to the nets within the network; a third program code mechanism for identifying critical nets; and a fourth program code mechanism for inserting net latches at the critical nets, wherein each of the net latches is controlled by the same enable signal that controls related enabled latches within the network.
Similarly, the method comprises the steps of identifying critical nets in the network, and subsequently placing net latches at each critical net, wherein each net latch is controlled by an enable signal that also controls a related enabled output latch.
Therefore, it is an advantage of the present invention to provide a method and system for eliminating the unnecessary toggling of nodes in a network.
It is therefore a further advantage of the present invention to provide a software program for modifying an existing logic network design.
It is therefore a further advantage of the present invention to reduce wasted power in a CMOS logic network.


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Benini et al. “Saving Power by Synthesizing Gated Clocks for Sequential Circuits,” IEEE Design and Test of Computers, Winter 1994, vol. 11, Issue 4, p. 32-41, Dec. 1994.

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