Metal gate stack with etch stop layer

Details Metal gate stack with etch stop layer Metal gate stack with etch stop layer

2002-10-18

2003-12-16

Le, Vu A. (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S656000, C438S737000, C438S738000, C438S742000

Reexamination Certificate

active

06664604

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing, and more particularly to the formation of metal gate electrodes.
BACKGROUND OF THE INVENTION
In the integrated circuit (IC) industry, metal-oxide semiconductor (MOS) transistors have typically been formed utilizing polysilicon gate electrodes. Polysilicon material has been preferred for use as an MOS gate electrode due to its thermal resistive properties (i.e., polysilicon can better withstand subsequent high-temperature processing). Polysilicon's robustness during high-temperature processing allows polysilicon to be annealed at high temperatures along with source and drain regions. Furthermore, polysilicon's ability to block the ion implantation of doped atoms into a channel region is advantageous. Due to the ion implantation blocking potential of polysilicon, polysilicon allows for the easy formation of self-aligned source and drain structures after gate patterning is completed.
However, polysilicon gate electrodes have certain disadvantages. For example, polysilicon gate electrodes are formed from semiconductor materials that suffer from higher resistivities than most metal materials. Therefore, polysilicon gate electrodes may operate at much slower speeds than gates made of metallic materials. To partially compensate for the high resistance, polysilicon materials often require extensive and expensive silicide processing in order to increase their speed of operation to acceptable levels.
Metal gates are therefore being investigated as replacements for polysilicon gates. Metal gates are fabricated in a manner that is similar to the fabrication processes for polysilicon gates. An exemplary layer structure is depicted in
FIG. 1A
of a metal gate structure. Gate oxide layer
12
is first deposited on a substrate
10
. A barrier layer
14
, made of titanium nitride (TiN), for example, is formed on the gate oxide layer
12
. The layer
14
is primarily chosen for appropriate workfunction properties which determine the threshold voltage of the transistor structure. The barrier layer also aids in the adhesion of the subsequently formed metal gate. The TiN can be deposited by conventional methodologies, such as physical vapor deposition (PVD). Alternate materials such as TaN, TaSi
x
N
y
, WN etc. may be used for this purpose.
A metal gate layer
16
is then formed on the barrier layer
14
. An exemplary material for the metal gate layer
16
is tungsten, although other materials may be used. The tungsten is deposited by conventional methodologies, such as physical vapor deposition.
A SiRN anti-reflective coating (ARC)
18
is formed on the metal gate layer
16
. This is followed by formation of a cap layer
20
over the ARC layer
18
. The cap layer
20
may comprise silicon nitride (SiN), for example. The anti-reflective coating
18
and the cap layer
20
aid in the patterning of the gate prior to the reactive ion etch process used to form the gate. Anti-reflective coatings
18
,
20
increase the resolution during the lithography process.
After the deposition of the layers
12
-
20
over the substrate
10
, the metal gate is now etched. This is accomplished by conventional patterning and etching techniques. The tungsten layer is typically etched with a fluorine containing chemistry, such as SF
6
/N
2
or SF
6
Cl
2
/N
2
, with WF
6
being the primary product species. The latter chemistry has yielded good profiles. In the latter case, an appropriate SF
6
/Cl
2
ratio may be chosen to provide the best profiles. The recipe may even be richer in Cl
2
than in SF
6
as required. It is desirable for the etch to have good selectivity to the TiN of the barrier layer
14
so that the tungsten can be cleared across the entire wafer without attacking the gate oxide. Hence, the TiN ideally serves as an etch stop layer during the etching of the tungsten. An ideal etching process is depicted in
FIG. 1B
, which shows the patterning of the metal gate electrode by an anisotropic reactive ion etch process, stopping on the TiN at the barrier layer
14
. However, this depiction is only an ideal depiction, as the TiN has proven in practice to be an inadequate etch stop layer. As depicted in
FIG. 1C
, when the tungsten is being cleared from the rest of the wafer, the TiN is completely etched on some parts of the wafer (indicated by reference numeral
22
in
FIG. 1C
) allowing the etchant to attack the gate oxide
12
. This occurs because TiN readily etches in the Cl
2
containing W etch chemistry. This results in the gate oxide being exposed either to the F from the W chemistry or being subject to the Cl-based TiN chemistry for the course of the TiN etch, both of which result in damage to the gate oxide. The use of endpoint monitors such as optical emission from W species to stop the W etch from proceeding once the W film clears also does not reliably solve this problem, since the thin TiN film continues to etch quickly while the endpoint is being detected. Thus, even though a TiN etch selective to gate oxide may be employed when W endpoint is detected, the attack of TiN during the W etch process itself makes this approach unreliable in practice. Simply increasing the TiN thickness itself is not practical owing to increases in stress leading to possible delamination and/or an increase in sheet resistance. The complete etching away of the TiN leads to degraded gate oxide and decreased yield.
Replacing the TiN with different etch stop material may detrimentally affect the work function of the TiN, and also may not exhibit the adhesion properties that are desirable in the TiN. However, there is a need for improved structure that allows the etching of tungsten with a Cl
2
/SF
6
/N
2
process that properly stops on the etch stop layer and protects the gate oxide across the wafer, without detrimentally affecting the work function of the metal gate.
SUMMARY OF THE INVENTION
This and other needs are met by the embodiments of the present invention which provide a method of forming a metal gate comprising the steps of forming a gate oxide on a substrate, forming a first metal layer on the gate oxide and forming an etch stop layer on the first metal layer. The etching need not completely stop on this etch stop material—indeed there is usually a finite amount of etching in plasmas due to physical ion bombardment. However, if the etch may be slowed down enough to permit termination of the W etch, an appropriate chemistry may be employed to etch TiN with sufficient selectivity to gate oxide, while being certain that no attack or punchthrough of the TiN layer had taken place in the W etch. The second metal layer is formed on the etch stop layer. The second metal layer is then etched to form a metal gate, with the etching stopping on the etch stop layer. The etch stop layer and the first metal layer are removed except under the second metal layer of the metal gate.
In certain embodiments of the invention, the first metal layer comprises TiN and the etch stop layer on top of the first metal layer comprises either aluminum or tantalum, depending on the nature of the W etch chemistry. If the W etch chemistry is F-rich, aluminum may be used as the etch stop layer owing to the low vapor pressure of AIF
3
. On the other hand, if the W etch chemistry is Cl-rich, the much lower vapor pressure of TaCl
5
as opposed to TaF
5
and WF
6
will also result in a significant slowdown of the etch rate, allowing the etch to be terminated when clearing of W is detected. Such layers have better etch selectivity than the TiN and can be made thin enough to not affect the work function of the TiN. Hence, the etching of the tungsten may proceed and stop at the etch stop layer, thereby assuredly protecting the gate oxide underlying the etch stop layer and the TiN of the first metal layer. A similar approach may also be used when TaN, TaSiN or WN for example are used as the underlying metal gates, since the F-component of the W etch will readily attack these materials as well as gate oxide. The use of an aluminum etch stop layer will p

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