Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-17
2003-10-21
Hu, Shouxiang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S412000, C257S751000, C257S763000
Reexamination Certificate
active
06635918
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and also to a method for manufacturing the same. More particularly, the invention relates to a technique which is suitably applicable to semiconductor integrated circuit devices which include a DRAM (dynamic random access memory) provided with a memory cell having a stacked capacitor structure wherein an information storage capacitor is arranged above a MISFET for memory cell selection.
The recent DRAM with a great capacity usually has a stacked capacitor structure, wherein an information storage capacitor is arranged above a memory cell selection MISFET, in order to compensate for a storage charge reduction of an information storage capacitor as will be caused by the miniaturization of the memory cells.
The information storage capacitor having the stacked capacitor structure is formed by successively superposing a storage electrode (lower electrode), a capacity insulating film(dielectric film), and a plate electrode (upper electrode). The storage electrode of the information storage capacitor is connected with one of the semiconductor regions (source region, drain region) of a memory selection MISFET of the n channel type. The plate electrode is constituted as a common electrode for a plurality of memory cells and is supplied with a given fixed potential (plate potential).
The other semiconductor region (source region, drain region) of the memory cell selection MISFET is, in turn, connected to bit line in order to a permit data to be written in and read out. The bit line is provided between the MISFET for memory cell selection and the information storage capacitor or above the information storage capacitor. The structure wherein the information storage capacitor is provided above the bit lines is called a “capacitor over bitline” (COB) structure.
A DRAM having such a COB structure is described, for example, in Japanese Laid-open Patent Application No. 7-122654 (corresponding to a U.S. patent application Ser. No. 08/297,039, assigned to Hitachi Ltd.), and Japanese Laid-open Patent Application No. 7-106437.
The DRAM disclosed in the Japanese Laid-open Patent Application No. 7-122654 includes bit lines which are formed of a polysilicon film (or polycide film) formed above the MISFET for memory cell selection wherein a gate electrode (word line) is formed of a built-up film (polycide film) of a polysilicon film and a tungsten silicide (WSix) film. An information storage capacitor which includes a storage electrode formed of a polysilicon, a capacitance insulating film constituted of a built-up film of a silicon oxide film and a silicon nitride film, and a plate electrode formed of a polysilicon film are provided above the bit lines. In addition, a common source line made of a first layer made of an Al (aluminium) film and a word line for a shunt are formed over the information storage capacitor.
The DRAM set out in the Japanese Laid-open Patent Application No. 7-106437 includes bit lines made of a polysilicide film and formed on the MISFET for memory cell selection whose gate electrode (word line) is made of a polysilicon film. The storage electrode or plate electrode of the information storage capacitor disposed above the bit lines and the first interconnection layer of a peripheral circuit are both formed of a metal material (e.g. Pt). Thus, the step of forming the electrode of the information storage capacitor and the step of forming the metallic interconnection of the peripheral circuit are performed commonly to simplify the manufacturing process.
SUMMARY OF THE INVENTION
The DRAM having the COB structure includes a gate electrode (word line) formed of polysilicon or polycide which has a resistance greater than metallic materials such as Al or W, so that a metallic interconnection (a word line for shunt) for backing the gate electrode is formed above the information storage capacitor, thereby reducing the delay of the gate. Since the bit line is constituted of polycide which is unable to simultaneously connect n-type and p-type semiconductor regions therewith, it is not possible to use a common interconnection for the bit lines and the peripheral circuit. To avoid this, the number of interconnection layers for both the memory arrays and the peripheral circuit increases, thus presenting a problem of increasing the number of manufacturing steps.
The common use of the interconnections for the bit lines and the peripheral circuit is not possible, so that the first interconnection layer of the peripheral circuit has to be formed as an upper layer relative to the bit lines. This causes a great aspect ratio (diameter/depth) of a connection hole for connecting the first interconnection layer and the MISFET's of the peripheral circuit, with the attendant problem that the formation of the connection hole becomes difficult and it also becomes difficult to embed or fill an interconnection material in the connection hole.
Where the gate electrode (word line) is formed of polysilicon or polycide with a high resistance, it is not possible to increase the number of memory cells capable of connection with one word driver or sense amplifier. More particularly, in order to reduce the delay of the gate, an increasing number of word drivers or sense amplifiers are necessary for connection to a given number of memory cells, so that there arises the problem that the chip size has to be increased, resulting in the lowering in degree of integration.
An object of the invention is to provide a technology capable of simplifying a process of manufacturing a DRAM having the COB structure.
Another object of the invention is to provide a technology for achieving a high-speed DRAM having the COB structure.
A further object of the invention is to provide a technology for achieving a high performance DRAM having the COB structure.
A still further object of the invention is to provide a technology for achieving a highly integrated DRAM having the COB structure.
The above and other objects, and features of the invention will become apparent from the description with reference to the accompanying drawings.
Typical inventions in this application are summarized below.
The semiconductor integrated circuit device according to one aspect of the inventions comprises a DRAM which includes a memory cell constituted of a MISFET for memory cell selection and an information storage capacitor formed on the MISFET, wherein a sheet resistance of a gate electrode of the MISFET for memory cell selection and a word line connected thereto, and a sheet resistance of a bit line connected to one of a source region and a drain region of the MISFET for memory cell selection, are, respectively, 2 &OHgr;/□ or below.
In the above one aspect of the invention, it is preferred that the sheet resistance of the gate electrode of the MISFET for memory cell selection and the word line connected thereto, and the sheet resistance of the bit line connected to one of a source region and a drain region of the MISFET for memory cell selection, are, respectively, 1 &OHgr;/□ or below.
It is also preferred that the gate electrode of the MISFET and the word line connected thereto are, respectively, made of a built-up film comprising, at least, a polysilicon film and a metallic film or a metal silicide film formed on the polysilicon film.
Preferably, the bit line is arranged above or over the MISFET for memory cell selection, and the information storage capacitor is arranged above or over the bit line.
The bit line should preferably be constituted of a built-up film which comprises, at least, a polysilicon film and a metallic film or a metal silicide film formed on the polysilicon film.
The sheet resistance of the interconnection formed on the information storage capacitor should preferably be equal to or smaller than that of the bit line.
A given interconnection layer of a peripheral circuit of the DRAM in the semiconductor integrated circuit device of the invention should preferably include an interconnection formed in the same manufacturin
Kajigaya Kazuhiko
Narui Seiji
Udagawa Tetsu
Yoshida Makoto
Hitachi , Ltd.
Hu Shouxiang
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