Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-16
2003-02-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06523163
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for forming pattern data and a method for writing a photomask with additional patterns and in particular to a method for processing data for forming data and writing data for a photomask with additional patterns which make pattern density of photomask uniform, and a method for writing a photomask with additional patterns which makes pattern density of photomask uniform wherein the photomask with additional patterns is used in the producing process of LSI for the main purpose of making the surface of wafer flat in the producing process of LSC.
2. Description of the Prior Art
Recently, it is being required to form a higher quality semiconductor by producing a more flat processing layer on the wafer in the production of the semiconductor, while high integration level and high function level are being required more and more for various LSIs typified by ASIC, due to the tendency toward highly efficient and lighter, thinner and smaller electronic equipment.
As an example in the art of producing a semiconductor having a flat processing layer and insulating layer on the wafer, it is disclosed in U.S. Pat. No. 5,597,668 that a photomask used for the production of the semiconductor is provided with additional patterns above and beyond a wiring pattern.
Herein, the significance of the additional patterns is described referring to FIG.
10
. For example, as shown in FIG.
10
(
a
)(i), for a processing layer (wiring layer) having patterns
511
of a high pattern density pattern portion
510
and a low pattern density pattern portion
512
, the thickness of the deposited layer (insulating layer) on the processing layers changes largely according to a change in the pattern density, as shown in FIG.
10
(
a
)(ii). As shown in FIG.
10
(
b
)(i), for a processing layer in which pattern density is made uniform by adding additional pattern
531
, the thickness of the deposited layer (insulating layer) is made uniform, as shown in FIG.
10
(
b
)(ii), wherein
530
designates additional pattern portions. It should be appreciated that FIG.
10
(
a
)(ii) and FIG.
10
(
b
)(ii) are sectional views showing the concept of the process of production of a semiconductor. FIG.
10
(
a
)(i) and FIG.
10
(
b
)(i) are views taken from the side E
1
of FIG.
10
(
a
)(ii) and from the side E
2
of FIG.
10
(
b
)(ii), respectively.
In general, it is known that when patterning such a deposited layer or a processing layer which is layered on the deposited layer (and according to the circumstances also the deposited layer), the more flat a deposited layer of the surface of wafer on which a pattern is transferred, the higher the obtained efficiency for transferring the pattern from photomask to wafer. Therefore, forming a processing layer with uniform pattern density enables improved efficiency of transferring the pattern from photomask to wafer.
In general, production of a wafer is finished by repeatedly layering a poly-silicon layer, an insulating layer, a wiring layer and an insulating layer on a wafer in order. However, since the poly-silicon and wiring layers are deposited only on a portion in which patterns exist, which is determined on the basis of design data, the surface of the processed wafer has a varying thickness depending on whether or not patterns exist. Since the insulating layer and the wiring layer are repeatedly layered on the wafer in order, the difference in height between portions in which no pattern exists and portions in which patterns exist gradually increases. As the shapes of patterns on the wafer become minute, the permitted limit of the difference in height narrows.
Further, it is known that when patterning of a photomask is made by means of an electron lithography system, even if data dimensions for patterning of the figures are the same, dimensions of the finished patterns on the photomask differ, depending on the pattern density of the patterns to be formed.
Heretofore, data of additional patterns for producing a photomask capable of generating additional patterns on the processing layer was generated by a method for generating additional patterns as shown in
FIG. 11
, wherein steps S
710
to S
740
designate processing steps. Referring to
FIG. 12
, the state of a wafer at each processing step of
FIG. 11
is illustrated.
In step S
710
of
FIG. 11
, areas in which additional patterns are arranged are first determined. In FIG.
12
(
a
), “dp” designates wiring patterns included in design data DP. Further, as shown in FIG.
12
(
b
), the minimum interval between wiring patterns and additional patterns is designated as “dist”. Figure NA which is over-sized with respect to wiring patterns dp is formed through the sizing figure processing. Area data AD having an area ad in which additional pattern areas are arranged is formed by subtracting the area of figure NA from the area da of the whole of design data DP through the Boolean NOT (FIG.
12
(
b
)).
In step S
720
additional patterns are generated in the whole area of FIG.
11
. Original arrangement of the additional patterns dt is formed in such a manner that the additional patterns are formed over the entire area ad (FIG.
12
(
c
)), wherein rectangular additional patterns are arranged in the second dimension.
The logical product of area ad in which additional patterns are arranged and arrangement of additional patterns dt is taken, by which arrangement of additional patterns are obtained from the arrangement of additional patterns included in the area ad in which additional patterns are to be arranged (FIG.
12
(
d
), S
730
)). The arrangement of additional patterns obtained through Boolean AND processing has broken additional patterns and fine additional patterns dd.
In step S
740
broken additional patterns dd are eliminated. Since fine figures in the production of a wafer are problematic, the final patterns have an arrangement of additional patterns which does not include broken additional patterns dd, by under-sizing and over-sizing through the sizing figure processing (
FIG. 12
(
e
)). Then, through the Boolean OR, the final pattern data FPO with additional patterns can be obtained from additional pattern data shown in FIG.
12
(
d
) or additional pattern data shown in FIG.
12
(
e
) and original design pattern data DP (FIG.
12
(
f
), S
750
). Namely, design pattern data dp and additional patterns dt are combined. The pattern data FPO with additional patterns is the data used to produce the photomask.
However, in the production of the photomask, a writing system is generally used in which a positive resist is applied and patterns are written on the positive resist by applying an electron beam or a laser beam to areas in which no pattern data exist.
In the conventional method for generating additional pattern data shown in
FIG. 11
, design data and additional patterns are formed independently. However, in the above-mentioned writing method using a positive resist, exposure of the design pattern results in writing of the whole additional patterns area so that additional patterns cannot be formed unless the additional patterns are written first. Therefore, in the conventional system for generating additional pattern data mentioned in the description of prior art, additional pattern data are formed independently. Therefore, it is needed to prepare one synthetic pattern data. However, as the design pattern is made more minute, data size of both design pattern data and additional pattern data becomes enormous. It is also necessary to form data having design pattern data and additional data together. Further, time is required for synthesizing of design data and additional data.
In order to simplify the system for generating additional pattern data shown in
FIG. 11
, an object is restricted only to the wiring layer, wherein the poly-silicon layer, also a deposited layer, is not taken into consideration. In conventional art, additional patterns cannot be generated to the poly-silicon layer. Further, in this system, an area designated for no addit
Bowers Brandon
Dainippon Printing Co., Ltd.
Flynn ,Thiel, Boutell & Tanis, P.C.
Siek Vuthe
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