Register file timing using static timing tools

Details Register file timing using static timing tools Register file timing using static timing tools

2000-08-10

2003-11-25

Heckler, Thomas M. (Department: 2185)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06654937

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuit design testing and more particularly to testing integrated circuits in complementary dual-rail systems using static timing tools.
BACKGROUND OF THE INVENTION
In designing integrated circuits (ICs), it is desired to be able to utilize efficient means in order to quantify and order every signal path within a design in terms of how long it takes the signal to propagate from its source to an end point and check that this propagation arrival against appropriate references is correct. Static timing software tools are used to accomplish that testing process. However, not every sort of design topology is able to be reconciled by the static timing tool. The present disclosure focuses upon the use of a static timing tool in testing topology that is pervasive in microprocessor and embedded designs including register files.
Previous approaches for simulating register files in static timers have primarily focused on building a model of the register file cell and simply avoid performing transistor analysis within it by enumerating desired input to output signal propagation and applying predetermined delay calculations. This competing approach requires that some other tool of circuit path analysis to be utilized in order to provide the delays through the register file. The motivation is to enable all possible paths to be found and ordered by delay or delay margin.
Thus there is a need to provide an improved method and apparatus to enable a static timing tool to determine the correct number of actual signal paths in a dual-rail system and report correct propagation delays in circuit where signal contention is detected.
SUMMARY OF THE INVENTION
A method and apparatus is provided for enabling a static timing tool to analyze and test register files in integrated circuits to find correct paths and ignore detected contention. This is achieved by utilizing pattern matching in the static timing tool and having the tool perform certain operations on the transistors of the pattern matched. The methodology includes disabling signal propagation through the memory element components, forcing predetermined internal nodes to be of inverse polarity, establishing signal direction through the circuit elements, and indicating that one or more of the predetermined nodes are not to be reported.


REFERENCES:
patent: 5872717 (1999-02-01), Yu et al.
patent: 5966521 (1999-10-01), Takeuchi et al.
patent: 6058252 (2000-05-01), Noll et al.
patent: 6522989 (2003-02-01), Gover et al.

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