Waveform generating device

Details Waveform generating device Waveform generating device

2000-09-08

2003-06-03

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Signal generation or waveform shaping

C702S070000, C702S073000, C702S082000, C702S125000

Reexamination Certificate

active

06574579

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a waveform generating apparatus for generating a test signal having a desired waveform and a semiconductor device testing apparatus using this waveform testing apparatus.
BACKGROUND ART
A waveform generating apparatus for generating a test signal having a desired waveform is used, for example, in a semiconductor device testing apparatus for testing a semiconductor device.
FIG. 26
shows an example of a conventional semiconductor device testing apparatus (hereinafter referred to as IC tester) for testing a semiconductor integrated circuit (including a large-scale integrated circuit (LSI); hereinafter referred to as IC) which is a typical example of a semiconductor device. This IC tester comprises, roughly speaking, a pattern generator PG, a timing generator
20
, a waveform shaping circuit FC, a driver DR, a level comparator LCP, and a logical comparator CP.
A main controller (not shown) mainly controls the pattern generator PG and the timing generator
20
. This main controller is generally constituted by a computer system, and controls the pattern generator PG, the timing generator
20
, and the like in accordance with a test program created by a user.
First, before a testing for an IC is started, various kinds of data are set by the main controller. After those various kinds of data have been set, the testing for an IC is started. By applying a test start instruction or command from the main controller to the pattern generator PG, the pattern generator PG starts to generate a pattern. The pattern generator PG supplies test pattern data (logical data) PAT to the waveform shaping circuit FC as well as supplies a test period signal PS (Period-Start) and a timing signal TS to the timing generator
20
in accordance with the control of the main controller.
In order for the timing generator
20
to add a predetermined amount of delay to the period signal PS supplied from the pattern generator PG, the timing generator
20
has a delay data memory
11
provided therein in which a plurality of timing (phase) delay data TD differing from one another have been previously stored. The timing generator
20
delays the period signal PS by an amount of delay corresponding to a timing delay data stored in an address of the delay data memory
11
specified by the supplied timing signal TS, and outputs the delayed period signal PS. This delayed period signal PS is supplied to the waveform shaping circuit FC as a timing pulse TPO, and also, is supplied to the logical comparator CP as a comparison clock pulse (strobe pulse) STRB.
The waveform shaping circuit FC generates a test pattern signal FCO having a desired real waveform on the basis of a test pattern data PAT supplied from the pattern generator PG and a timing pulse TPO supplied from the timing generator
20
. This test pattern signal FCO is amplified by the driver DR, and then is applied, as an input signal Si, to an IC under test (hereinafter referred to as DUT)
19
.
Here, in case that the DUT
19
is a memory IC (an IC the memory portion of which is the principal part), or in case of testing the memory portion of a system LSI (a large-scale integrated circuit in which the logic portion and the memory portion are present in mixture on one chip), or the like, the test pattern signal Si is stored in a predetermined memory cell of the DUT
19
, and the stored content is read out in a read cycle carried out later. On the contrary, in case that the DUT
19
is a logic IC (an IC the logic portion of which is the principal part), or in case of testing the logic portion of a system LSI, or the like, the result of a logical operation of the test pattern signal Si is outputted from the DUT
19
as a response signal So.
A response signal So read out from the DUT
19
is compared by the level comparator LCP with a reference voltage supplied from a comparison reference voltage source (not shown) to determine whether or not the response signal has a predetermined logical level, that is, a voltage SH of logical H (logical high) or a voltage SL of logical L (logical low). The response signal determined to have the predetermined logical level is sent, as a logical signal SH or SL, to the logical comparator CP where the response signal is compared with an expected value pattern signal EP outputted from the pattern generator PG to determine whether or not the DUT
19
has outputted a normal response signal.
If the response signal (SH or SL) does not coincide with the expected value pattern signal EP, a memory cell having an address of the DUT
19
from which the response signal was read out is determined to be defective (failure) in case that the memory portion of the DUT
19
is being tested, or in case that the DUT
19
is a memory IC, or the like, and a failure signal FAIL indicating that fact is generated from the logical comparator CP. Usually, when this failure signal FAIL is generated, a write operation of a failure data (in general, a signal of logical “1”) being applied to a data input terminal of a failure analysis memory (not shown) is enabled, and the failure data is stored in the failure analysis memory at an address thereof specified by an address signal being supplied to the failure analysis memory at that time. Generally, the same address signal as that has been applied to the DUT
19
is applied to the failure analysis memory, and hence the failure data is stored in an address of the failure analysis memory that is the same as that of the DUT
19
.
On the contrary, if the response signal coincides with the expected value pattern signal EP, a memory cell having an address of the DUT
19
from which the response signal was read out is determined to be normal, and a pass signal PASS indicating that fact is generated. Usually, this pass signal PASS is not stored in the failure analysis memory.
At a time point that the testing has been completed, the failure data stored in the failure analysis memory are read out therefrom, and then, for example, whether or not a relief or repair of the failure memory cells of the tested DUT
19
is possible is determined.
On the other hand, in case that the DUT
19
is a logic IC, or in case of testing the logic portion of a system LSI, or the like, when the response signal (SH or SL) does not accord with the expected value pattern signal EP, the test pattern signal having brought about that disaccord between the response signal and the expected value pattern signal, an address at which the test pattern signal has been generated, logical data outputted from a pin of the DUT
19
having outputted the response signal which does not accord with the expected value pattern signal EP, the expected value pattern data compared with the logical data at that time, and the like are stored in the failure analysis memory. Those data are utilized, after the completion of the test, in analyzing a cause of the failure occurrence mechanism, evaluating the tested LSI, or the like.
The timing generator
20
generates timing signals such as timing pulses TPO for defining respectively a rise timing and a fall timing of the waveform of the test pattern signal to be applied to the DUT
19
, a strobe pulse (clock pulse) STRB for defining a timing of a logical comparison between the response signal and the expected value pattern signal EP in the logical comparator CP, and the like.
Timings and periods for generating such timing signals are described in a test program created by the user, and the IC tester is constructed such that a test pattern signal is applied to the DUT
19
with an operating period and at a timing intended by the user to operate the DUT
19
so that whether the DUT
19
operates in normal condition or not can be tested.
Since the waveform generating apparatus mainly comprises the timing generator
20
and the waveform shaping circuit FC, several specific examples of the timing generator
20
will be first described.
FIG. 27
is a block diagram showing a first specific example of the timing generator
20
, and
FIG. 28
is a timing chart for explaining its operat

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