Synchronizing data between differing clock domains

Details Synchronizing data between differing clock domains Synchronizing data between differing clock domains

1999-08-23

2003-02-04

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C709S241000, C713S400000, C713S401000, C713S500000, C713S503000

Reexamination Certificate

active

06516362

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to communication among computer devices and more particularly to communication between computer devices operating at different clock frequencies and having skewed clock signals.
2. Description of the Related Art
Today's computer systems have been required to operate at ever increasing clock frequencies. One limiting factor to these faster performance levels has been the accuracy of the clock signals. Undesirable variation from ideal clock accuracy or skew was sought to be minimized. Today's clock generators have been required to deliver the shortest possible rise/fall times in propagation delay, tighter skew specifications and minimum jitter. As system cycle times decreased with higher performance systems, any slight variations even in terms of picoseconds (10
−12
sec) of integrated circuit outputs, or skew, become a more significant percentage of the overall timing budget. A particular area in the computer system where this has been very critical is the system clock.
The system clock must be distributed to various nodes across a board or backplane and yet exhibit little or no distortion. Thus, in addition to generating the various clock signals for the processor, or CPU, a clock generator must also provide other clock signals to peripheral interfaces such as video and graphics. Every picosecond of skew introduced into the clock line was propagated along the critical timing path.
The timing problems confronted in dealing with a single clocked system are compounded when multiple clock signals having different clock frequencies are introduced into the system. For example, a computer system is likely to have numerous independent processors each capable of being clocked at different frequencies. These differences in clock frequencies must be considered when defining timing requirements for communication between such computer devices. Typically, multiple frequency systems have been avoided where possible. However, in systems that require operation within at least two different frequency domains, the timing limitations caused by the differences in the frequency domains and the skew imposed on top of the clock signal have either directly limited the access speed for communication between devices operating at different frequencies or have been compensated by the introduction of multiple flip-flops to counteract the skew. Specifically, one mode of communication between devices operating at different frequencies has been achieved by quantitatively determining when the clock signals were expected to align. Because the different frequencies were known at the design stage, these timing calculations could be made ahead of time to form the proper system communications timing protocol. However, the required error timing ranges imposed on the read and write cycles to prevent setup and hold timing errors limited high speed applications. Alternatively, timing errors have been reduced through the use of multiple flip-flops to modify the timing of a transmitted signal by delaying a signal transmitted from one frequency domain gradually into the frequency domain of the recipient device. Likewise, however, the delay associated with the introduction of multiple flip-flop devices served as a performance limitation.
SUMMARY OF THE INVENTION
Briefly, a computer system is adapted to communicate between computer devices operating at different clock frequencies and to compensate for clock delay between computer devices operating at the same frequency. The computer system includes a transmission bus providing inter-connection among multiple peripheral devices. A synchronization signal is generated that indicates the phase between the different clock frequencies. Setup/hold timer issues are avoided by sampling signals transmitted from a device driven by a slower clock when the different clock signals are in phase. Similar setup/hold timing issues are avoided for signals transmitted from a device driven by the faster clock signal by sampling the received signals when the different clock signals are diametrically out of phase.
Further, the system compensates for clock skews up to almost a full clock cycle by providing a register that is clocked by a delayed clock signal. In this manner, a transmitted signal is received by the register in the normal clock frequency domain and released by the register in the delayed clock frequency domain and then received by the receiving device which is also clocked at the delayed clock frequency. Finally, return communications from the computer device operated at the delayed clock frequency to the computer device operated at the slower clock frequency is provided by a return register that is clocked at the delayed clock frequency. The return register releases return data during the next read cycle of the computer device operated at the slower clock frequency.


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