Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
Reexamination Certificate
1999-08-30
2003-02-11
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Incrementing, decrementing, or shifting circuitry
C711S213000, C711S214000, C711S215000, C711S218000
Reexamination Certificate
active
06519692
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to memory addressing by a computer processor, particularly a Digital Signal Processor.
BACKGROUND OF THE INVENTION
One of the basic functions performed by a digital processor is accessing a memory for data read and write. The memory is usually accessed by means of an address supplied to it by the processor. There are several methods of generating the data address inside the processor, these methods being known as addressing modes.
One of the most common addressing modes is the so-called “indirect addressing method”. In this method, one (or more) of the processor's registers, referred to as a pointer, holds the address of the memory location to be accessed. In many cases, and especially in a Digital Signal Processor, memory accesses are performed repeatedly one after the other. When using an indirect addressing mode, during each memory access the pointer used for the current access is updated with a new value corresponding to the next memory access, this operation being referred to as “post-modification”.
In order to support the use of the indirect addressing mode in a programmable processor, some predefined post-modification options are usually included in the processor's architecture and instruction set. These typically include modification of the pointer by +1, −1, +step (which can be a dedicated register by itself) etc. This mechanism is referred to as “internal post-modification”.
By way of example, the following operation performs an addition operation between the contents of a memory pointed to by rI, and another register named a
0
. The result is then written to the same register address a
0
, and the rI pointer is post-modified by +1 (i.e. its content is incremented):
Add(rI)+, a
0
A drawback with such an approach is that the internal post-modification mechanism is inherently limited to predefined options only. Thus, no provision is made for the processor to run an application requiring the pointer to be updated by an amount not provided for in the specific logic of the processor.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a mechanism which permits the pointer to be set by an application program to a value other than that dictated by internal post-modification.
This object is realized in accordance with a first aspect of the invention in a system comprising a processor coupled to a memory for providing a pointer in order to access a corresponding memory address, said pointer being updated by adding a predetermined increment according to logic integral with the processor, by a method for updating the pointer to a value other than that dictated by said logic so as to access an arbitrary memory address dictated by an application program accessing said processor; the method comprising:
(a) disabling the logic in respective of said pointer,
(b) processing the application program so as generate a successive memory address for accessing the memory, and
(c) setting the pointer to said successive memory address instead of incrementing the pointer by the predetermined increment dictated by said logic.
According to a second aspect of the invention, there is provided a processor comprising:
a plurality of internal registers each for storing a pointer therein for pointing to a memory address to be accessed by the pointer;
an internal post-modification unit for updating each of said pointers by adding a predetermined increment so as to assign a new address to the respective pointer;
a logic circuit for selectably disabling the internal post-modification unit in respective of one or more of said pointers and enabling external post-modification of the respective pointers.
Thus, according to the invention there is provided the possibility of external post-modification of each or any of the internal pointers. By such means, the user of a processor is able to update the pointer used for the next memory access to a value generated by an external mechanism that is application specific. This requires a dedicated interface to the user mechanism, and mode bit (or bits) used to override the predefined post-modification options supported by the instruction set, so that the address generated by the external mechanism will be used to update the pointer.
A principal feature of the invention is that it uses the post-modification options of the existing processor's instruction set, to access the external mechanism.
REFERENCES:
patent: 5032983 (1991-07-01), Fu et al.
patent: 5784712 (1998-07-01), Byers et al.
patent: 5987583 (1999-11-01), Triece et al.
patent: 6049858 (2000-04-01), Kolagotla et al.
Gross Yael
Ovadia Batsheva
Peretz Ronen
Sheier Moshe
D.S.P. Group Ltd.
Fish & Richardson P.C.
Kim Matthew
Peugh Brian R.
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