Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2000-12-14
2003-02-18
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S668000, C257S782000
Reexamination Certificate
active
06522020
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wafer-level package, and more particularly to a wafer-level package manufactured using a substrate and a lead frame to achieve improved reliability.
2. Description of the Related Art
Typically, semiconductor packages are manufactured by sawing a wafer to separate the individual semiconductor chips that had been simultaneously processed in the wafer state and then packaging the individual semiconductor chips. Taking into consideration the number of semiconductor chips obtained from one wafer, this typical package manufacturing method has drawbacks including a lengthened manufacturing time because the packaging process involves a number of unit processing steps such as die attaching, wire bonding, molding, trimming, and forming.
In order to solve these drawbacks, a new package manufacturing method has been proposed, in which a packaging process is preferentially carried out at a wafer level, with the individual devices being separated during subsequent steps. Semiconductor packages manufactured using such a method are called “wafer-level packages”.
Referring to
FIG. 1
, a conventional wafer-level package is illustrated. As shown in
FIG. 1
, a lower insulating layer
3
, which may be made of a dielectric material, is first coated over a wafer and the semiconductor chips
1
on that wafer. The bond pads
2
of each semiconductor chip
1
are then exposed by forming via holes in the lower dielectric layer
3
using conventional photolithography and etching processes. Metal patterns
4
associated with the semiconductor chips
1
are then formed on the lower dielectric layer
3
using conventional metal film deposition and etching processes such that each metal pattern
4
contacts the via holes over the bond pads
2
of the associated semiconductor chip
1
. An upper dielectric layer
5
is then formed over the metal patterns
4
and the exposed portion of the lower dielectric layer
3
. Portions of each metal pattern
4
remote from the bond pads
2
of the associated semiconductor chip
1
are then exposed through holes formed in the upper dielectric layer
5
using conventional photolithography and etching processes. The exposed portions of each metal pattern
4
define the ball lands on which solder balls
7
are to be mounted. Solder balls
7
are then mounted on the ball lands of each metal pattern
4
. In order to enhance the bonding strength of the solder balls
7
, an under bump metallurgy (UBM) layer
6
is formed on each ball land prior to the mounting of the solder balls
7
. The UBM layer
6
is made of a metal. This UBM layer
6
comes into contact with both the exposed ball land of the associated metal pattern
4
and the upper dielectric layer
5
.
All the above mentioned processing steps are carried out at the wafer level. The wafer is then sawn into individual semiconductor chips along scribe lines provided on the wafer. Thus, wafer-level packages are completely formed.
However, such a conventional wafer-level packaging is subject to various problems.
First, mechanical stress is concentrated at the interface between the upper dielectric layer and the UBM layer due to differences in the thermal expansion coefficients of the upper dielectric and UBM layers, comprising a macromolecular polymer and a metal respectively. For this reason, the conventional wafer level package exhibits an unstable and non-uniform signal flow between the semiconductor chip and the external signal input stage. Furthermore, even when the signal flow between the semiconductor chip and the external signal input stage is stable, delamination may occur at the interface between the upper dielectric layer and the UBM layer. Moisture may penetrate into the metal pattern via an interface portion, where the delamination occurs, thereby causing the metal pattern to be eroded. As a result, the signal flow between the semiconductor chip and the external signal input stage may be cut off. Also, the conventional wafer-level package exhibits a low bonding strength. This may result in a further instability of the signal flow between the semiconductor chip and the external signal input stage. Such a low bonding strength of solder balls results from the fact that those solder balls are subjected to severe shear stress as a result of differences in the thermal expansion coefficients of the semiconductor chip (approximately 3 ppm) and the associated circuit board (approximately 14 ppm), thereby causing cracks.
Second, it is difficult to improve the bonding strength of solder balls. Improvements in the solder ball bonding strength may be achieved by increasing the thickness of the primary stress absorbing layer, i.e., the lower insulating layer. However, increasing thickness of the lower insulating layer may result in increased package thickness, difficulty in conducting the etching process to expose the bonding pads, and/or difficulty in achieving good contact between the bond pads and the metal pattern. For this reason, there are practical difficulties in improving the solder ball bonding strength.
Third, it is difficult to apply the conventional wafer-level package to products requiring a high-speed operation. This is because the metal pattern is positioned just above the surface of the semiconductor chip, thereby resulting in an increase in capacitance that interferes with high-speed operation. Meanwhile, such increases in capacitance may be inhibited by increasing the spacing between the semiconductor chip and the metal pattern, that is, the thickness of the lower insulating layer. Again, however, this method involves the above mentioned problems, and so it has not yet been applied.
Fourth, the conventional wafer-level package may involve severe delamination in at the interface between laminated layers during the wafer separation process due to the fact that no encapsulation material is used. In severe cases, damage may occur at edge portion of the semiconductor chip. For this reason, the conventional wafer-level package exhibits degraded reliability and productivity.
SUMMARY OF THE INVENTION
Therefore, an object of the invention is to provide a wafer-level package capable of providing reliable signal flow between a semiconductor chip and an external signal input stage.
Another object of the invention is to provide a wafer-level package applicable to products requiring a high-speed operation.
Another object of the invention is to provide a wafer-level package capable of avoiding or reducing delamination at the interface between laminated elements during a wafer separation processing.
In accordance with the present invention, these objects are accomplished by providing a semiconductor chip having on its top surface a plurality of bond pads; a substrate bonded to the top surface of the semiconductor chip and provided with recess portions at each of opposite edge portions thereof not facing the bond pads while being provided with metal lines each extending to a portion of the substrate, arranged adjacent to an associated one of the bond pads, to a bottom surface of an associated one of the recess portions; metal wires electrically connecting the bond pads to the metal lines, respectively; a lead frame having inner leads each firmly fitted in an associated one of the recess portions of the substrate and electrically connected to an associated one of the metal lines by a solder, and outer leads formed to have a step structure; and an encapsulation material completely encapsulating the top surface of the semiconductor chip including the substrate and the metal wires while allowing only the outer leads of the lead frame to be exposed.
The present invention may be better understood with reference to the detailed description accompanying figures. The figures in particular are only for purposes of illustration and thus do not operate to unduly limit of the present invention.
REFERENCES:
patent: 6271586 (2001-08-01), Shen
Abraham Fetsum
Andujar Leonardo
Hyundai Electronics Industries Co,. Ltd.
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