Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2002-06-05
2003-12-30
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S189040
Reexamination Certificate
active
06671212
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of data writing and reading.
2. Background Art
Digital data is stored in memory devices as ones and zeros. Data is transferred into and out of a memory device via a conductive path called a “pin”. Data is written into the memory as a string of high and low signals that represent the ones and zeros. Each time there is a transition between the low and high signals, the efficiency of the memory device is reduced. However, because data is somewhat random, there is no easy way to control the data to reduce the number of transitions. This problem can be understood by a review of writing to and from memory devices.
FIG. 1
is a block diagram of a data source and a data receiver. The data source
100
communicates with the data receiver
102
via a bus
101
. Data is transferred in blocks of 8 bits called “bytes”. Each byte is sent to the data receiver
102
in parallel as 8 data signals on 8 lines with each signal line being high or low depending on the data being transmitted. For example, if a data value of one is sent, the bus line is at a high state. If the next signal sent is a zero, the bus line must be brought down to a low state to represent the new data. Then, if the succeeding signal is a one, the bus line must be again brought up to the high value. These changes of state are known as data transitions and require time and energy to achieve. Consider the following scenario, representing four bytes of data that are written to the data receiver
102
.
Data Byte
# of Transitions
00000000
—
11111111
8
10001000
6
01110111
6
The total number of data transitions in the 24 bits of bytes
2
,
3
, and
4
in the above example is 20, or 83%. (Note that this assumes that each line of the bus was in a low state when the original byte is sent). This results in time and power penalties in the operation of the data transfer system.
Data Inversion Scheme
The prior art has provided a scheme to reduce the number of data transitions in writing to a memory device known as “data inversion”. In the data inversion scheme, the number of data transitions between one byte and the next is determined and analyzed. If the number of transitions is greater than four, the data of the byte to be sent is inverted. In this way the number of transitions is made to be less than four. This scheme sets a bound of four on the greatest number of transitions that can occur from byte to byte, for a maximum of 50% transitions. The operation of the data inversion scheme is illustrated by reference to the table below.
Data Byte
Invert?
Data Byte Actually Sent
# of Transitions
00000000
—
00000000
—
11111111
Yes
00000000
0
10001000
No
10001000
2
01110111
Yes
10001000
0
After the first byte is sent, the next byte is examined to see how many transitions there would be if the byte was sent without inversion. Here, where the byte changes from all zeros to all ones, there would be 8 transitions. Since 8 is greater than four, the byte is inverted, becoming all zeros. When this byte is sent, there are no data transitions, since each line of the bus was already in the low state. Examining the next byte, it is compared to the actual byte sent (in this case the inverted byte) to determine the number of possible transitions. Without inversion, there will be two transitions, which is less than four, so the byte is sent without inversion. Comparing the next byte (01110111) to the byte that had been sent reveals 8 transitions if it is sent without inversion. Therefore the byte is inverted (to 10001000) and is sent with no transitions. Sending the same data using the inversion scheme results in only 2 transitions out of 24 bytes, or 8.3%. This improvement results in better and faster data transfer operation.
A disadvantage of the data inversion scheme is that it requires an extra bits to be sent with the data byte so that the data can be properly used or stored at the data receiver, as well as extra bits when data is read from the receiver. These extra bits require additional wiring for the bus, data sender and receiver, adding to the expense and complexity of a system.
SUMMARY OF THE INVENTION
The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value or vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during reading operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.
REFERENCES:
patent: 4667337 (1987-05-01), Fletcher
patent: 5630106 (1997-05-01), Ishibashi
patent: 5748902 (1998-05-01), Dalton et al.
patent: 5953272 (1999-09-01), Powell et al.
patent: 6046943 (2000-04-01), Walker
patent: 6335718 (2002-01-01), Hong et al.
patent: 2003/0041223 (2003-02-01), Yeh et al.
Drapkin Olge
Macri Joseph
Nagashima Osamu
Temkine Grigori
ATI Technologies Inc.
Coudert Brothers LLP
Harriman, II J. D.
Phung Anh
LandOfFree
Method and apparatus for data inversion in memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for data inversion in memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for data inversion in memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3147973