Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-02-22
2003-11-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06643834
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a technology for designing layout of analog cells.
BACKGROUND OF THE INVENTION
In a semiconductor integrated circuit (IC), in recent years, the scale is becoming larger, the precision is becoming higher, and automation of layout designing is being advanced. Particularly, automation of layout designing of a logic circuit using a CMOS process is being advanced by employing a cell-based designing method or an ECA designing method. On the other hand, since an analog circuit needs high-precision DC characteristics, even when automatic placement and routing is conducted so as to simply satisfy the design rule of a wafer process, in most cases, desired electric characteristics cannot be obtained. In order to automate the layout designing of an analog circuit, the designer has to set all of layout design constraints as information. Most of the design constraints to be set relate to pairing of devices and placement of the paired devices on target positions in a layout. Consequently, conventional layout designing of an analog circuit employs a method of setting various design constraints such as designation of pairing of devices by the designer before layout designing. The outline will be described hereinbelow.
FIG. 30
is a block diagram showing the configuration of a conventional analog cell layout designing apparatus. As shown in
FIG. 30
, the analog cell layout designing apparatus has a circuit diagram generating section
101
, a circuit diagram storing section
102
, a design constraint input section
103
, a design constraint data storing section
104
, a circuit connection information extracting section
105
, a circuit connection information storing section
106
, a layout cell storing section
107
, a process design rule storing section
108
, an automatic placing section
109
, a section
110
for storing layout after placement, an automatic routing section
111
, and a final layout storing section
112
.
When the designer draws an analog circuit by the circuit diagram generating section
101
, circuit diagram data corresponding to the analog circuit diagram generated is written into the circuit diagram storing section
102
. When the designer sets design constraints by the design constraint input section
103
, the set design constraint data is written into the design constraint data storing section
104
.
In the circuit connection information extracting section
105
, circuit connection information is extracted from the analog circuit diagram data stored in the circuit diagram storing section
102
in consideration of the design constraint data stored in the design constraint data storing section
104
, and the extracted circuit connection information including the design constraints is written into the circuit connection information storing section
106
.
In the automatic placing section
109
, on the basis of the circuit connection information including the design constraints stored in the circuit connection information storing section
106
, applicable layout cells are read from layout cells stored in the layout cell storing section
107
and placed in accordance with a process design rule stored in the process design rule storing section
108
. After completion of the placement, the placed layout cells are written in the section
110
for storing the layout after placement.
In the automatic routing section
111
, routing of the layout cells stored in the section
110
for storing layout after placement is conducted according to the process design rule stored in the process design rule storing section
108
, and a result of the execution is written into the final layout storing section
112
.
The above-described analog cell layout designing method is realized by an automatic layout tool for analog cells, which is commercially available at present. As an idea of automating designing of layout of analog cells (blocks) from an analog circuit, a method of adding the layout design constraints to connection information of a circuit diagram, outputting the resultant, inputting the resultant to an automatic placing section, and reflecting the resultant in a layout is known. For example, Japanese Patent Application Laid-Open (JP-A) No. 7-73217 (device automatic placement apparatus) discloses a technique of separately providing a memory in which a pairing rule is stored and adding the design constraints read from the memory to connection information extracted from the circuit diagram.
The design constraints set in the design constraint input section
103
by the designer are, for example, settings (1) to (3) as described hereinbelow.
(1) To obtain an accurate voltage value and an accurate current value, for example, a setting of dividing a voltage as a reference (source voltage) by a plurality of resistive elements, each having an accurate zero-power resistance ratio, is made. For example, JP-A No. 5-129519 discloses a method of placing resistors so as to be symmetrical with respect to a line and so as to be perpendicular to a line of stress by a molding resin in order to obtain an accurate zero-power resistance ratio in layout design of resistors.
(2) In a current mirror circuit as shown in
FIG. 31A
, in order to obtain an accurate current ratio, a setting of constructing the current mirror circuit by a plurality of transistor devices having an accurate transistor size (area) ratio is made.
(3) Further, in designing the layout of a current mirror circuit as shown in
FIG. 31A
, a setting operation is performed as follows.
First, as shown in
FIG. 31A
, the designer draws up a list of the necessary number of devices from a circuit diagram.
FIG. 31A
shows three bipolar transistor devices of the same type. One of them is diode-connected. Each of the other two transistors has a normal transistor configuration. As shown in
FIG. 31B
, the designer considers the configuration of a current mirror circuit including the three bipolar transistor cells.
FIG. 31B
shows the current mirror circuit in which bipolar transistors B and C whose collectors are connected to each other are connected in parallel to a diode-connected bipolar transistor device A. The bases and emitters of the transistor devices are commonly connected to each other. Subsequently, as shown in
FIG. 31C
, the designer makes a setting placing the diode-connected bipolar transistor device A on a center line
120
and placing the bipolar transistor devices B and C whose collectors are connected to each other symmetrically on the right and left sides of the bipolar transistor device A.
However, the design constraints as described above are required irrespective of the circuit scale. Even in the case of a small-scaled analog circuit, the number of design constraints to be set is very large. Therefore, for the designer, much effort to make a setting for a memory or a circuit diagram is required. In many cases, considerable skill is required.
As a result, conventionally, automation of the layout designing of an analog circuit is delayed. Even designing analog cells in an actual IC occupies 60 to 70% of the turnaround time in designing a whole layout.
It is prime task to realize automatic setting of design constraints. For this purpose, at a stage before circuit connection information is input to the automatic placing section, a pre-process for adding information regarding dividing devices or the like to the circuit connection information is necessary. The question is how to realize it.
SUMMARY OF THE INVENTION
It is an object of the invention is to obtain a method of and an apparatus for designing layout of analog cells, capable of increasing layout designing precision and reducing a work of setting design constraints of the designer by automatically predicting design constraints of analog cell layout from circuit diagram data irrespective of the skill of the designer. It is another object of this invention to provide a computer readable recording medium that stores a computer program which when executed on a computer easily realizes the method according to the present
Koyama Takashi
Satoh Takao
Senoh Takeshi
Lee Granvill D.
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
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