Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-27
2003-06-03
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S308000, C257S310000
Reexamination Certificate
active
06573553
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically to a semiconductor device characterized by a junction structure between an adhesion improving layer and a capacitor dielectric film used in a storage capacitor formed in a DRAM (Dynamic Random Access Memory) or an FeRAM (Ferroelectric RAM), and a method for fabricating the same.
Recently, as semiconductor devices are more highly integrated and have larger capacities, design rules (line/space) have become increasingly precise. Accordingly, the semiconductor devices, e.g., DRAMs (Dynamic Random Access Memories) have widths of the wiring layers decreased, and the contact plugs connecting the storage nodes which are to be the lower connection electrodes of the storage capacitors to the source regions have smaller diameters.
Such the DRAM comprises cell regions each including one transistor and one storage capacitor, for storing 1-bit information. The storage capacitor comprises a lower electrode called a storage node, an upper electrode called a cell plate, and a capacitor dielectric film sandwiched between the upper and the lower electrodes.
In the conventional DRAM, an electrode material of the storage node and the cell plate is doped polycrystalline silicon, and the capacitor dielectric film is ON film (a composite film of SiO
2
and Si
3
N
4
) formed by thermally oxidizing the surface of a thin CVD nitride film.
The storage node is formed in a projected electrode structure to use as a capacitor not only the upper surface but also the side surfaces, whereby a sufficient capacitance can be obtained for a limited space (floor area). This has a background that the capacitance cannot be lowered below a prescribed capacitance, e.g., about 30 fF in order to cope with alpha radiation and decrease of the source voltage.
In addition, DRAMs have been developed with the integration improved by about 4 times every three years, i.e., the micronization improved; the projected structure of the storage capacitor, i.e., the projected structure of the storage node tends to become higher and higher so that a sufficient surface area can be ensured for a decreased capacitor floor area.
However, as the storage capacitor structure becomes higher, a height difference from the peripheral circuit region becomes larger. This resultantly causes a problem that the wiring layer becomes thin at the step, and the wiring becomes less reliable, and, in the exposing step, a problem of a depth of focus that the higher region and the lower region cannot be simultaneously focused.
On the other hand, although the above-described problems can be solved by planarizing with an insulation film to be equalized the height with the higher surface, there occur additional problems that contact holes in the peripheral circuit regions become deeper, making the etching difficult and that the contact holes of such high aspect ratio cannot be filled with a metal electrode material of low resistance.
Then, a material having a higher dielectric constant, i.e., a high dielectric constant film is required in place of the conventional ON film (a composite film of SiO
2
and Si
3
N
4
) as the capacitor dielectric film. Such the high dielectric constant film is used to thereby obtain a higher capacitance per a unit area. Studies of obtaining a required capacitance without increasing a height of the projected structure of the storage capacitor are made. This produces an advantage of simplifying steps of the fabrication.
As such the high dielectric constant film, the use of Ta
2
O
5
film, SBT (SrBi
2
Ta
2
O
9
) film, BST ((Ba,Sr)TiO
3
) film, etc. are studied. These high dielectric constant materials are basically oxides, and have a problem that when these films are deprived of oxygen, these films become conductive, and leak current tends to flow in the films.
DRAMs store information in charges stored in the storage capacitors. Seriously, increase of leak current means extinction of information stored in the DRAMS.
The storage node and the cell plate of the conventional storage capacitor are formed of polycrystalline silicon. Polycrystalline silicon can be easily deprived of oxygen. In using a high dielectric constant film as the capacitor dielectric film, it is vital to use an electrode material which take place of polycrystalline silicon.
An electrode material suitable for such the high dielectric constant film must satisfy the following (1) to (6) requirements:
(1) Oxygen defect which is a cause for depriving a high dielectric constant film of oxygen to cause leak current does not take place.
(2) An electrode material itself does not diffuse in the high dielectric constant film to cause deterioration of the high dielectric constant film.
(3) An electrode material is able to withstand high-temperature annealing for crystallizing the high dielectric constant film.
(4) The electrode material can be easily etched.
(5) An electrode material has a resistance as low as possible.
(6) An electrode material has good adhesion with a base insulation film, so that peeling does not take place after heat treatment.
However, it is very difficult to satisfy all the six requirements from (1) to (6), and no electrode material which satisfy all of the requirements has been so far found. Electrode materials, for example, Ru (Ruthenium) and RuO (Ruthenium Oxide), can satisfy, to some extent, the requirements (1) to (5) but does not satisfy the requirement (6).
That is, a Ru film and a RuO film have a defect that they tend to peel from the insulation film.
Then, in order to solve such defect of the peeling of these electrode films, which is their only one defect, it is considered to provide below such electrode materials an adhesion improving layer having good adhesion with the base insulation film for the prevention of the pealing of the electrode materials. As such the adhesion improving layer, TiN, WN, and Ta, etc. are prospective.
Here, with reference to
FIGS. 38A and 38B
, the storage capacitor of the conventional DRAM using Ru as the storage node and having the adhesion improving layer will be explained.
FIG. 38B
is a plan view of the DRAM at the time that a lower plug
75
of the DRAM is formed.
FIG. 38A
is a sectional view of the DRAM. In
FIG. 38A
, the layer structure up to a first inter-layer insulation film
69
is a sectional view along the one-dot chain line B-B′ in FIG.
38
B, the layer structure from a second inter-layer insulation film
72
to a third inter-layer insulation film
74
is a sectional view along the one-dot line A-A′ in
FIG. 38B
, and the layer structure thereabove is a sectional view again along the one-dot chain line B-B′ in FIG.
38
B. In
FIG. 38A
, the layer structure below the third inter-layer insulation film is represented conveniently by A-A′ to simplify the showing.
In
FIG. 38A
, for convenience, a bit line
73
is shown, shorted to the lower plug
75
, but they are positionally isolated from each other as shown in FIG.
38
B.
Reference will be made to
FIGS. 38A and 38B
.
First, a device isolation oxide film
62
is formed by selective oxidation in a prescribed region of a p-type silicon substrate
61
. Then, the exposed surface of the p-type silicon substrate
61
surrounded by the device isolation oxide film
62
is thermally oxidized to form a gate oxide film
63
. Next, a non-doped polycrystalline silicon film is deposited, and an impurity, such as P (phosphorus) or others, is ion-implanted. Then, the polycrystalline silicon layer is etched into a prescribed pattern to form gate electrodes
64
and word lines
65
, which are extensions of the gate electrodes
64
.
Actually, an SiO
2
film or an Si
3
N
4
film as a protection film is provided by CVD method on the gate electrodes
64
.
Then, as the gate electrodes
64
as a mask, an impurity, such as As (arsenic), P or others, is ionimplanted to form an n
+
-type drain region
67
and an n
+
-type source region
68
. Then, an SiO
2
film is deposited on the entire surfa
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Nguyen Cuong Quang
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