Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1995-01-20
1996-01-16
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Bad bit
36523008, G11C 700
Patent
active
054854253
ABSTRACT:
There is provided a semiconductor memory device having a redundant column. This memory device has a redundant column disposed in the direction of the Y-system address, a ROM accessed by using an X-system address, a Y-system address signal having a defective cell included in the cells therein being electrically written into the ROM, a comparator circuit for comparing a signal read out from this ROM with a Y-system address signal and outputting a coincidence signal upon coincidence, and a defect relieving circuit responsive to output of the coincidence signal from this comparator circuit to cause selection of the redundant column of Y system instead of the Y-system address selection device.
REFERENCES:
patent: 4051354 (1977-09-01), Choate
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4803656 (1989-02-01), Takemae
patent: 5122987 (1992-06-01), Kihara
patent: 5168468 (1992-12-01), Magome et al.
Iwai Hidetoshi
Muranaka Masaya
Nasu Takumi
Sukegawa Shunichi
Hitachi , Ltd.
Texas Instruments Incorporated
Zarabian A.
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