Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-17
2003-06-10
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C257S329000
Reexamination Certificate
active
06576952
ABSTRACT:
BACKGROUND OF THE INVENTION
At present, semiconductor process technology is capable of creating features having dimensions well into the submicron range. At this level of miniaturization, feature size variations due to what is commonly referred to as the “optical proximity effect” can become significant. In general, proximity effects are variations in feature dimensions that are due to the proximity of other nearby features. In particular, optical proximity effects are proximity effects that occur during optical lithography. As a result of optical proximity effects, the size of a given feature can vary based on its spacing from other features.
Among the phenomena contributing to optical proximity effects are diffraction patterns associated with imaged features. One example of an optical proximity effect is the difference in dimension that can occur between an isolated printed line and a printed line in a dense array of equal lines.
Specific consequences of optical proximity effects include situations where internal features, which are surrounded by other features, and peripheral features, which are not, differ substantially. (Under these circumstances, optical proximity effects are frequently referred to as optical edge effects.) For example, at present, during photolithographic processes at submicron feature sizes, peripheral photoresist features frequently display a significant optical edge effect. As a result, etched silicon trenches, among other features, are frequently and adversely affected. Accordingly, devices employing etched silicon trenches, such as trench DMOSFETS (double diffused metal oxide semiconductor field effect transistors), trench Schottky barrier rectifiers, DRAM (dynamic random access memory) devices, and devices in which trenches are used to isolate separate integrated circuits, are likewise frequently and adversely effected by the optical edge effect.
An example of such an edge effect is presented in
FIGS. 1A and 1B
. These figures illustrate a situation where trenches are etched using apertures between the photoresist features. More specifically, as seen in
FIG. 1A
, a silicon substrate
10
is provided with photoresist features
15
a
,
15
b
,
15
c
,
15
d
via an optical lithography process. As shown in this figure, the internal features
15
a
,
15
b
and
15
c
, each of which is positioned between other features (the feature to the left of internal feature
15
a
is not shown here), have substantially vertical sidewalls. Unfortunately, as a consequence of the optical edge effect discussed herein, peripheral feature
15
d
, which is not positioned between other features, has a substantially oblique sidewall as shown.
FIG. 1B
illustrates the results that are obtained after subjecting the photoresist-patterned silicon substrate to an etch step. As can be seen in this figure, due to the substantially vertical nature of the sidewalls associated with photoresist features
15
a
,
15
b
and
15
c
, silicon sidewalls
10
a
,
10
b
and
10
c
are also substantially vertical. In contrast, due to the substantially oblique nature of the sidewalls associated with photoresist feature
15
d
, silicon sidewall
10
d
is also substantially oblique, resulting in a sharp corner at the trench bottom.
In other instances, a silicon substrate is etched using a silicon oxide or silicon nitride photomask. Referring to
FIG. 2A
, a silicon oxide or nitride layer is etched via photoresist features
15
a
,
15
b
,
15
c
,
15
d
, to form silicon oxide or silicon nitride features
17
a
,
17
b
,
17
c
,
17
c
on silicon substrate
10
. As shown in this figure, the internal photoresist features
15
a
,
15
b
,
15
c
, each of which is positioned between other photoresist features, have substantially vertical sidewalls, while the peripheral photoresist feature
15
d
, which is not positioned between other photoresist features, has a substantially oblique sidewall. The same is true of the silicon oxide or nitride features
17
a
-
17
c
. Photoresist features
15
a
,
15
b
,
15
c
and
15
d
are then removed, leaving only oxide or nitride features
17
a
,
17
b
,
17
c
and
17
c
.
FIG. 2B
illustrates the result of etching the silicon substrate
10
using silicon oxide or silicon nitride features
17
a
,
17
b
,
17
c
and
17
c
alone as masking features. As can be seen, the results are largely the same as those achieved when the substrate
10
is etched using photoresist features
15
a
,
15
b
,
15
c
and
15
d
(see FIG.
1
B). Specifically, due to the substantially vertical nature of the sidewalls associated with silicon oxide or silicon nitride features
17
a
,
17
b
,
17
c
, silicon sidewalls
10
a
,
10
b
and
10
c
are also substantially vertical. Furthermore, silicon oxide or silicon nitride feature
17
c
has a substantially oblique sidewall, which results in a trench feature having a substantially oblique silicon sidewall
10
d
and an accompanying sharp corner at the trench bottom.
In still other instances, a silicon substrate is etched through a mask defined by both photoresist features and silicon oxide or nitride features. As shown in
FIG. 3
, the internal photoresist features
15
a
,
15
b
,
15
c
, each of which is positioned between other photoresist features, have substantially vertical sidewalls, while the peripheral photoresist feature
15
d
, which is not positioned between other photoresist features, has a substantially oblique sidewall as shown. The same is true of the silicon oxide or nitride features
17
a
-
17
d
. As to the silicon substrate
10
, due to the substantially vertical nature of the sidewalls associated with features
15
a
/
17
a
,
15
b
/
17
b
and
15
c
/
17
c
, silicon sidewalls
10
a
,
10
b
and
10
c
are also substantially vertical. In contrast, due to fact that feature
15
d
/
17
c
is oblique and is comprised of a combination of photoresist and oxide or nitride, a sharp corner is formed at the trench bottom, as was observed in connection with
FIGS. 1 and 2B
. Moreover, the silicon substrate
10
is undercut at the interface that is formed with the oxide or nitride feature
17
d.
In each of the above cases, the optical proximity effect produces undesirable trench characteristics, including sloping sidewalls and sharp-cornered bottoms. Accordingly, there is a need in the art to address optical proximity effects on etched trench features.
Others have addressed problems arising from optical proximity effects in DRAM applications by putting dummy trenches around the cells. See, e.g., J. Fung Chen, Tom Laidig, Kurt E. Wampler and Roger Caldwell, “Practical Method for Full-Chip Optical Proximity Correction,” SPIE Proceedings, Vol. 3051,1997; J. Fung Chen, Tom Laidig, Kurt E. Wampler and Roger Caldwell, “An OPC Roadmap to 0.14 mm Design Rules,” paper presented at BACUS, 1997; J. Li, D. Bernard, J. Rey, V. Boksha, “Model-Based Optical Proximity Correction Including Photo-resist Effects,” Proc. SPIE, V. 3051, 1997, P. 643-651; N. Shamma, F. Sporon-Fiedler, E. Lin, “A Method for Correction of Proximity Effect in Optical Lithography,” KTI Microlithography Seminar Interface '91, P. 145; Chris A. Mack, “Evaluating Proximity Effects Using 3-D Optical Lithography Simulation,” Semiconductor International July 1996 P. 237; O. Otto etc., “Automated optical proximity correction—a rule-based approach,” SPIE Proceedings, V. 2197, P. 278, 1994; A. Komblit etc., “Role of etch pattern fidelity in the printing of optical proximity corrected photomasks,” EIPB'95, 1995.
However, a need nonetheless remains in the art for alternative methods of addressing these problems.
SUMMARY OF THE INVENTION
These and other needs in the art are addressed by the present invention.
According to a first aspect of the present invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and
Hshieh Fwu-Iuan
So Koon Chong
Tsui Yan Man
Bonham, Esq. David B.
Dickey Thomas L
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Tran Minh Loan
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