Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-30
2003-02-18
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S413000, C257S382000, C257S383000, C257S324000, C257S350000
Reexamination Certificate
active
06521963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing a semiconductor device, and particularly to a semiconductor device having an electrode made of a stacked structure of metal/(poly)silicon and a manufacturing method thereof.
2. Description of the Background Art
FIG. 30
shows a longitudinal section of an MOS transistor
101
P as a semiconductor device according to a first conventional technique, which has a polycide gate composed of a stacked structure of silicide/polysilicon. The MOS transistor
101
P may be called “a DRAM transistor” since it is used as a transistor in the memory cell area in a DRAM (Dynamic Random Access Memory).
As shown in
FIG. 30
, the silicon substrate
1
P is sectioned by trench isolations
2
P into areas in which MOS transistors are formed. A gate insulating film
3
P is formed on the main surface of the silicon substrate
1
P, which is made of a film of silicon oxide obtained by applying thermal oxidation to the main surface.
A gate electrode GE
1
P is formed on the gate insulating film
3
P, which is comprised of a polysilicon layer
4
P and a silicide layer
60
P stacked in this order as the main materials. Silicon oxide films or reoxidation films
14
P are formed on the sides of the polysilicon layer
4
P.
This polycide gate structure is formed as described below. First, polysilicon and silicide are sequentially stacked and a TEOS oxide film (not shown) is formed thereon. The TEOS oxide film is then patterned by photolithography and the silicide layer and the polysilicon layer are etched together by using the patterned TEOS oxide film as a hard mask in anisotropic etching. Subsequently, reoxidation (thermal oxidation) is applied to the sides of the etched polysilicon layer. The gate electrode GE
1
P composed of the polysilicon layer
4
P, the reoxidation films
14
P, and the silicide layer
60
P is thus formed as shown in FIG.
30
.
Side wall spacers or spacers
7
P are formed in contact with the gate insulating film
3
P and the sides of the polysilicon layer
4
P and the silicide
60
P. The spacers
7
P are formed by forming a dielectric film, such as a TEOS oxide film or silicon nitride film, to cover the gate electrode GE
1
P and then etching it back.
The structure also has source/drain extension regions
6
P and source/drain regions
8
P (hereinafter these are also referred to as “source/drain regions
9
P” together) formed in the main surface of the silicon substrate
1
P. These regions
6
P and
8
P are formed by ion implantation.
Although not shown in
FIG. 30
, interlayer film is formed to cover the gate electrode GE
1
P and interconnections connected to the gate electrode GE
1
P and the like are formed on the interlayer film.
Next,
FIG. 31
shows a longitudinal section of an MOS transistor
102
P as a semiconductor device according to a second conventional technique. The MOS transistor
102
P may be referred to as “a logic transistor” since it is applied to a logic circuit, for example.
As shown in
FIG. 31
, the MOS transistor
102
P has a gate electrode GE
2
P and salicide layers or silicide layers
10
P as source/drain region electrodes, both of so-called salicide structure formed by self-aligned silicidation. The structure is equivalent to that of the above-described MOS transistor
101
P (see
FIG. 30
) in other respects. The MOS transistor
102
P is manufactured by the following method.
First, the main surface of the silicon substrate
1
P is thermally oxidized to form a silicon oxide film (which forms the gate insulating film
3
P later). Then a polysilicon layer and a TEOS oxide film are stacked on the exposed surface of the silicon oxide film and the TEOS oxide film is patterned by photolithography. Subsequently, the polysilicon layer is etched by using the patterned TEOS oxide film as a hard mask in anisotropic etching. Next, the source/drain extension regions
6
P are formed by ion implantation and then reoxidation is applied to the sides of the etched polysilicon layer to form reoxidation films
14
P. The spacers
7
P are then formed and the source/drain regions
8
P are formed by ion implantation.
Subsequently, the TEOS oxide film used as a hard mask is etched to expose the upper surface of the polysilicon layer. Next, a metal film, such as cobalt (Co), is formed entirely over the silicon substrate
1
P and it is annealed. This annealing causes silicidation (salicidation) of the metal film and the upper surface of the polysilicon layer and the exposed surface of the silicon substrate
1
P, which forms the silicide layers or salicide layers
70
P and
10
P. Next the unreacted metal film is removed by etching. Thus the gate electrode GE
2
P composed of the silicide layer
70
P, the polysilicon layer
4
P, and the reoxidation films
14
P is formed as shown in FIG.
31
.
Next,
FIG. 32
shows a longitudinal section of a semiconductor device (which may be referred to as a hybrid transistor)
104
P as a semiconductor device according to a third conventional technique, which has the MOS transistor
101
P and an MOS transistor
103
P corresponding to the MOS transistor
102
P. While the MOS transistor
103
P is the same as the above-described MOS transistor (logic transistor)
102
P in that it is applied to a logic circuit, for example, it differs from the MOS transistor
102
P in that the gate electrode GE
1
P of the MOS transistor (DRAM transistor)
101
P is applied to its gate electrode. A method for manufacturing the hybrid transistor
104
P will now be described.
As shown in
FIG. 32
, the regions for formation of the MOS transistors
101
P and
103
P are sectioned by the trench isolations
2
P. The region in which the DRAM transistor
101
P is formed is referred to as a memory cell area and the region in which the logic transistor
103
P is formed is referred to as a logic area.
Subsequently, thermal oxidation is applied to the main surface of the silicon substrate
1
P to form a silicon oxide film which forms the gate insulating film
3
P later. Next, the memory cell area is covered with a resist mask by photolithography, and the silicon oxide film in the logic area is removed by wet etching. Then, the resist mask is removed, and thermal oxidation is performed again to form a thin silicon oxide film in the logic area and a thick silicon oxide film in the memory cell area. After that, the gate electrodes GE
1
P are formed in the two MOS transistors
101
P and
103
P, as described in the method for manufacturing the MOS transistor
101
P. In the following manufacturing steps, basically, given manufacturing process step is applied to one of the memory cell area and the logic area with the other covered by resist mask or the like. For example, in the process steps for forming the source/drain regions
9
P in the MOS transistors
101
P and
103
P, ion implantation is applied sequentially to the memory cell area and the logic area. Then, with a mask formed on it except in the vicinities of the source/drain regions
9
P in the logic area, a metal film, e.g. cobalt (Co), is deposited on the entirety of the silicon substrate
1
P. The salicide layers
10
P are then formed by annealing on the source/drain regions
8
P (or
9
P) in the logic area. Unreacted metal film is then etched away.
The MOS transistors
101
P to
104
P according to the conventional techniques have the following problems (1) to (5).
<Problem (1): Problems due to Resistance of Silicide Layer>
The polycide gate electrodes GEIP and GE
2
P of the conventional MOS transistors
101
P to
104
P have higher gate resistance than a gate electrode composed of a stacked structure of polysilicon layer/metal layer (hereinafter referred to as a polymetal gate (electrode)). The conventional MOS transistors
101
P to
104
P therefore have problems of large interconnection delay, generating much heat, etc.
<Problem (2): Problem in Formation of Gate electrode>
The gate electrodes GE
1
P and GE
2
P of the conventional MOS transistors
101
P to
104
P are difficult to form, since they
Kitazawa Masashi
Ota Kazunobu
Shirahata Masayoshi
Chaudhuri Olik
Louie Wai-Sing
Mitsubishi Denki & Kabushiki Kaisha
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