Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
1999-08-13
2003-02-04
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S453000, C438S218000, C438S225000, C438S233000, C438S297000, C257S647000, C257S774000, C257S305000
Reexamination Certificate
active
06514834
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a semiconductor device improved so that leak current can be reduced.
The present invention further relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIG. 52
is a circuit diagram of a memory array of a conventional dynamic random access memory (DRAM).
FIG. 53
is a diagram showing waveforms of array operation of the conventional DRAM.
Referring to these figures, a memory cell array of the conventional DRAM includes a word line (WL), a bit line (BL), a bit line isolation (BLI), a sense drive line (SN), a bit line precharge (VBL), a restore drive line (SP), a memory cell, an N channel-sense amplifier (Nch-SA), an equalizer, and a P channel-restore amplifier (Pch-RA).
Information is stored in the memory cell. A place in which reading/writing is to be carried out is designated by selection of a word line. Reading.or writing is carried out by selection of a specified bit line.
FIG. 54
is a sectional view of the memory cell of the conventional DRAM. In the surface of a P-type semiconductor substrate
1
, provided is a field oxide film
2
which isolates an active region
3
from other active regions with its end portion
2
a surrounding active region
3
. An active layer
4
which is an impurity diffusion layer is provided in the surface of active region
3
. A gate electrode (word line)
5
is provided on active region
3
. An interlayer insulating film
6
is provided on semiconductor substrate
1
so as to cover gate electrode
5
. A contact hole
7
exposing the surface of active layer
4
is provided in interlayer insulating film
6
. Contact hole
7
is filled with a storage node B which is a conductor is electrically connected to the surface of active layer
4
. The surface of storage node
8
is covered with a dielectric film
9
. A cell plate electrode
10
is provided so as to cover storage node
8
with dielectric film
9
interposed therebetween. A bit line
12
is connected to an active layer
11
.
In the memory cell of the DRAM, information is held by storing charge in dielectric film
9
sandwiched by storage node
8
and cell plate
10
.
The stored charge leaks to decrease in accordance with time. When much of the stored charge leaks, accurate information cannot be read out, causing malfunction of the device.
Leakage current is mostly caused by defects in semiconductor substrate
1
.
Description will be given of the leakage current in more detail.
FIG. 55
is a layout diagram of a DRAM. In
FIG. 55
, a contour
13
represents an end portion of a mask forming an active region, which will be described in more detail.
More specifically, referring to
FIG. 57A
, in order to form active region
3
on semiconductor substrate
1
, a mask
14
of a silicon nitride film is formed on active region
3
.
Referring to
FIG. 57B
, the surface of semiconductor substrate
1
is thermally oxidized using mask
14
to form field oxide film
2
. At this time, an end portion of field oxide film
2
goes under mask
14
to form a bird's beak portion
22
.
Referring to
FIG. 57C
, when mask
14
is removed, field oxide film
2
is formed which is divided into a body region
16
having an approximately constant thickness and a bird's beak region
15
having a thickness gradually decreased in the direction toward active region
3
.
In
FIG. 55
, contour
13
represents an end portion
13
of mask
14
. In other words, referring to
FIGS. 55 and 57C
, contour
13
represents the boundary between body region
16
and bird's beak region
15
.
In
FIG. 55
, a contour
17
represents an opening portion of a resist mask for formation of a storage node contact hole, which will be described in more detail. More specifically, referring to
FIG. 58A
, in order to form a contact hole in interlayer insulating film
6
, a resist mask
18
having a predetermined opening portion
17
is formed on interlayer insulating film
6
. Referring to
FIG. 58B
, interlayer insulating film
6
is etched using resist mask
18
to form contact hole
7
. Contour
17
represents an end portion of the above-described opening portion
17
.
FIG. 56
is a sectional view of a memory cell taken in the same direction as the direction of the,
56
—
56
line in FIG.
55
. Field oxide film
2
is formed in the surface of semiconductor substrate
1
. Active layer
4
is formed in the surface of active region
3
. Interlayer insulating film
6
is formed on semiconductor substrate
1
so as to cover active layer
4
. Contact hole
7
exposing the surface of active layer
4
is formed in interlayer insulating film
6
. Contact hole
7
is filled with storage node
8
. A depletion layer
20
extends from active layer
4
.
As described above, leakage current is mostly caused by a defect
21
in semiconductor substrate
1
. Referring to
FIG. 57B
, when field oxide film
2
is formed in the surface of semiconductor substrate
1
, much stress is applied directly under bird's beak portion
22
. Therefore, a lot of defects
21
are formed in the vicinity of the boundary between bird's beak portion
22
and semiconductor substrate
1
. Metal ions generated in the manufacturing process of a semiconductor device are trapped in defects
21
. Referring to
FIG. 56
, when depletion layer
20
extending from active layer
4
comes in contact with defects
21
, a leakage current component other than leakage current in the direction opposite to the case of a normal PN junction is added, which in turn rapidly decreases charge stored in the memory cell. This is a problem of the conventional DRAM.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device which is improved so that leakage current can be suppressed.
Another object of the present invention is to provide a semiconductor device which is improved so that leakage current caused by a defect in a substrate can be suppressed.
Still another object of the present invention is to provide a dynamic random access memory which is improved so that a hold time of information can be increased.
A further object of the present invention is to provide a dynamic random access memory which is improved so that charge stored in a memory cell is not decreased.
A further object of the present invention is to provide a method of manufacturing the above-described semiconductor device.
The semiconductor device according to the first aspect of the present invention includes a semiconductor substrate. On the semiconductor substrate, provided is a field oxide film which isolates an active region from other active regions; with its end portion surrounding the active region. An interlayer insulating film is provided on the semiconductor substrate so as to cover the active region. A contact hole exposing a part of the surface of the active region is provided in the interlayer insulating film. The contact hole is filled with a conductor electrically connected to the surface of the active region. The end portion of the field oxide film has a surface perpendicular or approximately perpendicular with respect to the surface of the semiconductor substrate.
The semiconductor device according to the second aspect of the present invention includes a semiconductor substrate. On the semiconductor substrate, provided is a field oxide film which isolates an active region from other active regions with its end portion surrounding the active region. An active layer is provided in the surface of the active region. An interlayer insulating film is provided on the semiconductor substrate so as to cover the active region. A contact hole exposing the surface of the active layer is provided in the interlayer insulating film. The contact hole is filled with a conductor in contact with the active layer. The active layer is spaced from the end portion of the field oxide film so as not to be in contact with the end portion of the field oxide film.
The semiconductor device according t
Berezny Neal
Fahmy Wael
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Method of manufacturing a semiconductor device having a low... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device having a low..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device having a low... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3144636