Self-testing of magneto-resistive memory arrays

Details Self-testing of magneto-resistive memory arrays Self-testing of magneto-resistive memory arrays

2000-02-04

2003-06-24

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06584589

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the testing of memory circuits, and in particular to built-in self test circuitry for magneto-resistive memory (MRAM) arrays.
BACKGROUND OF THE INVENTION
In the production of large and complex integrated circuits one of the important considerations is the testability of the circuit. Because of flaws and inaccuracies which can affect the integrated circuits during fabrication it is important to be able to test the fabricated circuits before they are dispatched for use, so that faulty IC's can be discarded or, in some instances, corrected. Often such testing is performed by external circuitry, however the efficiency of testing can be increased if testing circuitry is included in the IC. This is referred to a built-in self test circuitry.
The documents referred to below describe some techniques for built-in self test in large scale integrated circuits.
1. M. Abramovici, et al; Digital Systems Testing and Testable Design; Chapter 9: “Design for testability”; Rockville, Md.; Computer Science Press; 1990
2. E. B. Eichelberger & T. W. Williams; “A Logic Design Structure for LSI Testability”; Journal of Design Automation and Fault Tolerant Computing; Vol. 2, pp 165-178, May 1978
35. Dasqupta, et al; “A variation of LSSD and its Implementation in Design and Test Pattern Generation in VLSI”; Proc. IEEE ITC; 1982; pp 63-66
Built-in self testing of memory circuits can be particularly advantageous because a large number of test vectors may be required in order to test a large memory array, which can involve substantial testing time for external circuitry. One of the testing procedures which is useful for memory arrays such as DRAM and SRAM is referred to as a pattern test, where a predetermined pattern (e.g. a checkerboard pattern) of data is written to the array and then the array is read to determine if the retrieved data matches the pattern that was written.
A new form of memory array which is being developed is referred to as magnetic random access memory (MRAM), and has the potential to be fabricated in arrays having storage capacities of many giga-bits. Because of the structure of MRAM elements and arrays, the size of the arrays and the data I/O structure thereof, built-in self test circuits which have been developed for SRAM and DRAM are inapplicable or insufficient for the purposes of MRAM.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, there is provided a built-in self testing system for a magneto-resistive memory array integrated circuit including a first resistance specification testing circuit coupled to the bitlines of the memory array for testing the resistance of each memory cell in the memory array to determine if the resistance thereof is within predetermined upper and lower limits.
Preferably the resistance specification testing circuit compares a signal generated from each respective memory cell with first and second predetermined timing signals representing the predetermined upper and lower memory cell resistance specification limits.
In the preferred form of the invention the resistance specification testing circuit is incorporated in sense amplifier circuitry of the integrated circuit. The resistance specification testing circuit may include a charge integrating circuit arranged to integrate charge according to sensing current through a memory cell under test. A threshold circuit may be coupled to provide a binary output from the integrating element, and a switching circuit can be coupled to provide the binary output to a scan register of the sense amplifier in accordance with the first and second predetermined timing signals. The contents of the scan register can then be used to indicate whether the memory cell passes or fails the resistance specification test.
A second testing circuit may be coupled to the rows of memory cells in the memory array and arranged to detect shorted memory cells and open row addressing lines in the respective array rows. Preferably the second testing circuit comprises a wired-OR circuit coupled with the memory array rows to provide input and coupled to provide output to a row error flag register which records if any shorted cell or open row addressing line is detected in the memory array.
A third testing circuit may be coupled to a scan register of the memory array and arranged to write a predetermined data pattern into the memory array, read out data from the memory array, and compare the data read out with the data written in.
In a preferred form of the invention the third testing circuit is coupled with the first testing circuit through a wired-OR circuit to combine the outputs thereof into an error flag column register. The error flag column register can be used to record a number of errors detected by the first and third testing circuits for each row in the memory array in order to determine if the number of errors for each respective row is greater than a predetermined permissible number.
In accordance with the present invention there is also provided a built-in self testing system for a magneto-resistive random access memory (MRAM) integrated circuit having an array of memory cells, the memory cells each coupled between a respective row line and column line of the array, with sense amplifiers being coupled to the column lines of the array to sense data stored in the memory cells and a scan register coupled to receive output from the sense amplifiers and provide input for the memory cells in the array. The built-in self-testing system includes a first testing circuit comprising a resistance specification testing circuit coupled to the respective sense amplifiers for testing the resistance of each memory cell in the memory array to determine if the resistance thereof is within predetermined upper and lower limits. The built-in self testing system in this case also includes a second testing circuit coupled to the row lines of the memory array for detecting shorted memory cells and open row addressing lines in the respective array rows. This form of the built-in self testing system further includes a third testing circuit coupled to the scan register of the memory array and arranged to write a predetermined data pattern into the memory array, read out data from the memory array, and compare the data read out with the data written in.
A preferred form of the built-in self testing system further includes a testing state machine circuit coupled to control the first, second and third testing circuits to carry out respective first, second and third tests on the memory array.
Preferably the first and second predetermined timing signals are generated by said testing state machine circuit.
In accordance with another form of the invention there is provided a method for providing a built-in self testing capability for a magneto-resistive random access memory (MRAM) integrated circuit having an array of memory cells with at least one sense amplifier for sensing data stored in the memory cells. The method includes the steps of: using the sense amplifier to generate a current signal representing a sensing current through a memory cell in the array; time integrating the current signal and applying a threshold thereto to produce a binary output; sampling the binary output at first and second times; and registering the memory cell as outside predetermined resistance specifications based on the first and second sampled binary outputs.
The preferred embodiments of the present invention provide several advantages over the prior art. For example, conventional memory testing will require a significant time to test each chip that will result in making the MRAM test costs relatively high. Built-in self tests as found on SRAM and DRAM chips can be used to reduce testing time, but are limited to pattern tests and do not consider the special test requirements of MRAM arrays. This embodiments of the present invention utilize the write data and read data sense circuits found in MRAM arrays to create a wide range of built-in self test features which takes advantage

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