Semiconductor memory device with simultaneous data line...

Details Semiconductor memory device with simultaneous data line... Semiconductor memory device with simultaneous data line...

2001-10-09

2003-06-24

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030, C365S230060, C365S201000

Reexamination Certificate

active

06584022

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a semiconductor memory device having a redundancy structure.
2. Description of the Background Art
In order to repair defective memory cells to improve the yield, a conventional semiconductor memory device includes redundant memory cells to substitute for the defective memory cell.
In recent years, the demand for a large bus width to improve the data transfer speed is great. There is the tendency of a larger data line width and a relatively smaller column address. Particularly in a dynamic random access memory (DRAM embedded with a logic circuit directed to system-on-chip, there is the demand of increasing the bus width from 32 bits to 256 bits and reducing the column address from 256 bits to 16 bits.
In a conventional semiconductor memory device, repair of a defective memory cell was carried out by exchanging the bit lines through a column address. When the column address is small, a high repair rate cannot be achieved unless a relatively large amount of redundant memory cells are prepared.
To this end, the method of arranging a redundant memory cell and a redundant data line connected to that redundant memory cell to exchange the defective data line with a redundant data line is being employed.
In a logic-embedded DRAM, the method is employed of providing a large internal bus width and selecting a required bus width using a column address at the connection to an external source so as to accommodate a variety of bus widths.
An example of a conventional semiconductor memory device
5000
with a redundancy structure will be described with reference to FIG.
64
. Semiconductor memory device
5000
includes a memory cell array
500
with a plurality of memory cells arranged in a matrix, a plurality of normal data line pairs
501
connected to memory cells via a sense amplifier, a redundant data line pair
502
, a row decoder
510
decoding an input row address to carry out selection in a row direction, a column address decoder
511
decoding an input column address for output, a shift redundancy circuit
512
including position information of a defective data line, an IO select circuit
503
selecting a data line, a read amplifier•write driver unit
504
, and an IO shift circuit
505
.
IO select circuit
503
selects a data line pair to be used according to the output of column address decoder
511
. Referring to
FIG. 65
, IO select circuit
503
is formed of a plurality of switches. Half of normal data line pairs LIO(
0
), LIO(
0
), . . . are connected to read amplifier•write driver unit
504
. Redundant data line pair SLIO(
0
), /SLIO(
0
) or SLIO(
1
), SLIO(
1
) is connected to read amplifier•write driver unit
504
.
Read amplifier•write driver unit
504
includes a plurality of read amplifier•write drivers RW (read amplifier R, write driver W). By read amplifier•write driver unit
504
, the data of the selected data line pair are transmitted to internal data lines DB(
0
), and redundant internal data line SDB, or the data of internal data lines DB(
0
), and redundant internal data line SDB are transmitted to the selected data line pair.
In IO shift circuit
505
, the connection between the internal data line and the data input/output pin (external data line) is shifted to remove a defective data line according to the data line shift method, as shown in FIG.
66
. More specifically, the defective data line is replaced with an adjacent data line. The data line used for replacement is further replaced with an adjacent data line. By repeating replacement between adjacent data lines, the last data line is replaced with the redundant data line. As a result, data lines other than the defective data line are connected to data input/output pins (external data line) DQ(
0
)-DQ(n).
Thus, data of a selected memory cell is output to an external source. In a write operation, data is written into a selected memory cell through an opposite path.
According to the structure of the conventional semiconductor memory device, the pass through the switch circuit to switch the data lines and the data line switch circuit for redundancy replacement is inevitable, causing delay in data transfer.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a semiconductor memory device capable of high speed data transfer in a semiconductor memory device having a redundancy structure.
According to an aspect of the present invention, a semiconductor memory device includes a memory cell array with a plurality of memory cells arranged in a matrix, a plurality of data lines with a redundant data line and a normal data line to read out data or write in data from/to the memory cell array, a plurality of external data lines to transfer data with an external source, and a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with a plurality of external data lines and a shift operation of shifting the connection of a data line to be coupled to a plurality of external data lines according to an external address and data line information related to a defective data line in the normal data lines.
Preferably, the plurality of data lines are divided into a plurality of blocks. The data line switch circuit includes a decoder decoding an external address and data line information, and a plurality of select circuits arranged between a plurality of blocks and the plurality of external data lines respectively. Each of the plurality of select circuits carries out a select operation and a shift operation simultaneously according to the output of the decoder. Each of the plurality of select circuits shares some of the data lines with an adjacent select circuit.
Each of the plurality of select circuits includes a plurality of transfer gates provided between a corresponding data line and a corresponding external data line to be open/closed according to the output of the decoder.
According to the semiconductor memory device having a redundant data line of the present aspect, execution of the data line shift redundancy scheme and selection of a data line specified by an address can be carried out simultaneously. Therefore, high speed data transfer is allowed.
According to another aspect of the present invention, a semiconductor memory device includes a memory cell array with a plurality of memory cells arranged in a matrix, a plurality of data lines with a redundant data line and a normal data line to read out or write in data from or to the memory cell array, and a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with a plurality of external data lines according to an external address and a replace operation of replacing a defective data line in the data line to be coupled with a redundant data line according to data line information related to a defective data line.
Preferably, the plurality of normal data lines are divided into a plurality of blocks. The data line switch circuit includes a decoder decoding an external address and data line information, and a plurality of select circuits. Each of the plurality of select circuits carries out simultaneously a select operation and a replace operation.
Particularly, each of the plurality of select circuits includes a plurality of transfer gates that are open/closed according to the output of the decoder, provided between a redundant data line and corresponding normal data line and a corresponding external data line.
According to the semiconductor memory device having a redundant data line of the present aspect, data transfer can be carried out at high speed since the data line replace operation and the data line select operation are carried out simultaneously.
According to a further aspect of the present invention, a semiconductor memory device includes a memory cell array with a plurality of memory cells arranged in a matrix, a plurality of data lines with a redundant d

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