Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2001-02-16
2003-11-18
Lane, Jack A. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S133000, C711S159000
Reexamination Certificate
active
06651153
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention relates generally to methods of predicting the performance of a cache memory in a computer system, and more specifically, to methods of predicting the performance of a cache memory in a proposed computer system having a proposed computer system architecture and configuration.
2. Description of the Prior Art
Modern computer systems can have a wide variety of computer architectures and configurations. To optimize efficiency, a computer system should have an architecture and configuration that is suitable for an expected load. If the architecture or configuration is excessive for a particular load, some of the computer resources will be wasted. If the architecture or configuration is not sufficiently robust for a particular load, the computer system will not provide adequate performance.
A high performance desktop computer designed for multi-media or graphical applications often has a standard PC architecture, with a relatively large amount of Random Access Memory (RAM), large hard drives, and one or more processors with fairly high clock rates. Multi-media and graphical applications are often computational and/or memory intensive, thereby requiring relatively large amount of memory and processing capability. In contrast, a desktop computer system designed for office use may have a standard PC architecture, but will often have far less RAM, a smaller hard drive and a single processor with less performance. The reduced computer resources of office type systems is appropriate because of the fairly light load of many office applications such as word processing.
For more complex computer systems, such as on-line transaction processing systems, both the architecture and the configuration of the computer system are often designed to accommodate the expected load. The overall throughput of such systems is often dependent on a number of inter-related factors including, for example, the overall architecture of the computer system, the configuration of the computer resources with the architecture, and the expected load and load type.
The architecture of a computer system may include, for example, the location of cache memory, the number of cache memory levels, the location of main memory, the location of processors within the system, the internal bus structure, the I/O structure, as well as other architectural details. The configuration of computer resources within the architecture may include, for example, the size and speed of each level of cache memory, and the number and speed of the processors.
The expected load should be taken into account when designing a computer system, and in particular, when selecting an architecture and/or configuration for the computer system. During the development of a computer system, the developer typically has some idea of the expected load for the system. Often, the expected load for the computer system is estimated by examining the software that will be run on the system. To help design a robust computer system that can efficiently handle the expected loads, it is important for the developer to have some way of evaluating the performance of a proposed computer system based on the expected load, before the system is actually completely developed. This may allow the developer to evaluate many different computer architecture and/or configurations before selecting a particular architecture and/or configuration for the particular application.
A primary way for a developer to evaluate and predict computer system performance is to develop computer performance models. Such models have traditionally been developed using either probabilistic evaluation (analytic models) or discrete event simulation programs (simulation models).
An analytic model is often defined to be a model that accepts moment estimators (such as mean arrival and service times) as its input and, using a closed form or iterative method, produces moment estimators for the desired statistics (such as average wait time). Analytic modeling has proven to be applicable in a wide range of computer system performance evaluation problems, and is the primary method used commercially today.
There are some fundamental drawbacks to analytic modeling. One drawback is that not all discrete systems can be evaluated in this manner. Furthermore, direct measurements have shown that many computer systems seriously violate the underlying assumptions of analytic models. Cache memory systems have presented a particular problem because of the large quantity and diverse nature of today's cache memory workloads, which create arrival and service distributions which are not only extremely variable, but do not conform to those conventionally assumed for these models. Thus, such models provide severely limited results, which limits the ability of a developer to predict the performance of different cache memory configurations in a proposed computer system. Also, the actual distributions of the analytic modeling parameters often must be simplified, which further compromises the accuracy of the results.
Simulation models are primarily useful in studying computer performance at a high level of detail. A simulation model may be defined to be a model which accepts a set of measured or generated events (such as arrival or service requests) as its input and produces performance data corresponding thereto. Unfortunately, the processing requirements needed to run the simulations is related to the level of detail of such models. Because many of today's systems are very large and complex, detailed simulation is rarely used commercially because of the inordinate amount of processing time required to produce performance data. Also, and as is the case for analytic modeling, the ability of simulation models to predict the performance of different cache memory configurations is severely limited because of the large quantity and diverse nature of modern day cache memory workloads.
Statistical techniques have also been used to augment and assist conventional analytic and simulation approaches, and also to aid in their evaluation. For example, statistical techniques have been used to provide a sub-model portion of, for example, an overall cache memory simulation model. While such usage of statistical modeling offers the possibility of reducing the complexity and processor requirements of some simulation models, it often does not reduce the simulations times to desirable levels unless the sub-models are oversimplified, which results in reduced accuracy.
Performance projections for processors and memory subsystems are often critically dependent upon a correct understanding of the workloads which are imposed on such systems. In order to accurately predict the performance of a proposed system to assist in selecting among the various design tradeoffs, some prior art systems collect instruction streams (i.e., “traces”) that statistically represent actual workloads. By using traces that represent a fixed workload as input to a system model that allows variations on some hardware parameters, such as the number of processors, some developers hope to predict performance for that workload versus the number of processors.
A limitation of using representative trace data is that the traces can become very large, even for fairly simple instruction streams. A number of methods for minimizing the length of the trace data are disclosed in, for example, U.S. patent application Ser. No. 09/747,050, filed Dec. 21, 2000, entitled “System and Method for High Speed, Low Cost Address and Bus Signal Tracing”, U.S. patent application Ser. No. 09/745,813, filed Dec. 21, 2000, entitled “High Speed Processor Interconnect Tracing Compaction Using Selectable Triggers”, and U.S. patent application Ser. No. 09/747,046, filed Dec. 21, 2000, entitled “Coordination of Multiple Processor Bus Tracings for Enable Study of Multiprocessor Multi-Bus Computer Systems”, all of which are assigned to the assignee of the present invention and all of which are incorporated herein by reference. Even using
Crompton Seager & Tufte LLC
Johnson Charles A.
Lane Jack A.
Starr Mark T.
Unisys Corporation
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