Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-06-12
2003-02-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S778000, C438S780000, C438S781000, C438S788000, C438S622000, C438S623000, C438S624000
Reexamination Certificate
active
06521548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a passivation layer, and more particularly, a method of forming a quickly on-line cured SOD passivation layer in an oxygen controlled environment so as to increase throughput.
2. Description of the Prior Art
In a semiconductor manufacturing process, the structure of an integration circuit(IC) on a semiconductor wafer is complete after the main process steps, such as metallization and planarization. Since the main process steps are completed, these integration circuits are vulnerable to damage caused by unintentional collision or exposure to moisture. Therefore a passivation layer is formed on the surface of the semiconductor wafer in order to protect the integrated circuits.
Moreover, since the metal lines will give the surface of the integration circuits an unleveled profile, this means gaps between metal lines cannot be filled by the passivation layer and so voids are formed. The passivation layer according to the prior art utilizes spin-on-glass(SOG) material. The spin-on-glass is a silicon dioxide in solution and has good step coverage ability and flow ability. It forms the passivation layer better than the passivation layer made by a typical plasma-enhanced chemical vapor deposition(PECVD) process or high density plasma chemical vapor deposition(HDPCVD) in terms of planarization ability. The spin-on-glass passivation layer according to the prior art utilizes the spin coating technique, that comprises exposing a specific amount of silicon dioxide solution to the surface of the semiconductor wafer, performing a bake process generally termed as soft bake in order to evaporate the solvent, further performing a curing process with a higher temperature in order to transform the silicon dioxide solution to a more pure silicon dioxide in solid form.
The prior art curing process can be performed in a furnace and the semiconductor wafer after soft bake normally needs to be cured at a temperature ranging from 400 to 450° C. for from 30 minutes to several hours. Moreover, in U.S. Pat. No. 5,270,267, Ouellet et al. proposes another method of curing the passivation layer that involves curing the SOG passivation layer in a plasma environment at a temperature ranging from 200 to 400° C. in order to expel organic volatile substances, SiO Hand water molecules from the SOG passivation layer. However, the method proposed by Ouellet et al. is more expensive and also takes a long processing duration from 30 to 60 minutes which does not increase throughput. Furthermore, the prior art method is a off-line process, in other words, the semiconductor wafer needs to be stored for a period of time after the soft bake process before the hard bake (curing) process, which results in a process difference.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a spin-on-passivation layer quickly so as to shorten the time required by a curing process thereby increasing throughput.
It is therefore another objective of the present invention to provide an on-line method of forming the low dielectric constant spin-on-passivation layer quickly so as to make the product with consistency and high throughput.
In the first preferred embodiment of the present invention, a semiconductor substrate is firstly provided and at least two neighboring metal lines are formed on it, followed by a plasma-enhanced chemical vapor deposition(PECVD) process performed so as to form a PE oxide layer on the semiconductor substrate, the PE oxide layer covers the surface of the neighboring two metal lines and the gap between the neighboring two metal lines uniformly. Thereafter a SOD layer is formed on the PE oxide layer and fills in the gap. After that the semiconductor substrate is heated directly by at least a first w hot plate with the temperature fixed at a first predetermined temperature to expel the solvent from the SOD layer. Finally the semiconductor substrate is directly heated by utilizing a second hot plate with a temperature fixed at a second predetermined temperature in order to cure the SOD layer for a predetermined time. The second hot plate is in an air sealed chamber and the oxygen content is controlled under 100 ppm by way of a nitrogen purge, the predetermined time is less than or equal to 10 minutes.
It is an advantage of the present invention to form the spin-on-passivation layer quickly with an on-line method so as to shorten the time required by the curing process and thereby increase the throughput.
REFERENCES:
patent: 5270267 (1993-12-01), Ouellet
patent: 6372666 (2002-04-01), Ramos et al.
Gurley Lynne A.
Hsu Winston
Macronix International Co. Ltd.
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