Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-23
2003-02-11
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S551000
Reexamination Certificate
active
06518180
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a pattern for use in steps of manufacturing a semiconductor device including a logic integrated circuit (IC) and also to a method for forming a mask.
BACKGROUND ART
Higher performance and integration of a semiconductor integrated circuit (LSI) has been achieved by making a circuit pattern finer. In particular, with respect to a logic LSI, its operation speed (operation frequency) has been improved by reducing a transistor gate length (Lg). With an enlarged chip scale and complicated system, however, a total wiring length within a chip has been abruptly increased, thus resulting in that a speed reduction (interconnect delay) caused by a wiring resistance and capacity governs the entire circuit performance. For the purpose of solving this problem, it becomes important to reduce a chip scale and to suppress the total wiring length by making smaller an interconnect pitch (wiring pitch) (a minimum spacing between centers of adjacent wiring lines or wiring period).
In the circuit formation, optical lithography (reduction projection exposure) is currently used, and its resolution is improved by reducing the wavelength of exposure light and increasing a numerical aperture (NA) of a projection lens. With respect to the above wiring pitch, 0.8-0.5 &mgr;m is currently attained with use of a KrF excimer laser exposure apparatus (having a wavelength of 248 nm), and it is considered to be able to attain about 0.4-0.35 &mgr;m with use of an ArF excimer laser exposure apparatus (having a wavelength of 193 nm). However, it is expected difficult to realize a smaller wiring pitch than the above level with use of the conventional reduction projection exposure method using far-infrared ray. As a method for realizing a finer pattern, there has been studied an electron beam direct writing (EBDW) method or an X-ray proximity exposure method. In the electron beam direct writing method, however, an enormous amount of time is generally required because individual patterns are sequentially written. In order to solve this problem, there is studied a cell projection method which can collectively transfer certain scales of patterns (e.g., having an about 5 &mgr;m square). In this method, however, since the types of settable patterns are restricted, this method is not necessarily effective for a random interconnect pattern of a logic LSI or the like which requires a very large number of types of patterns. (In this connection, it is assumed in this specification that the word “random” is used to mean not iterative or cyclical.) Also there is studied a SCALPEL (SCattering with Angular Limitation Projection Electron-Beam Lithography) method which can scanningly expose a large-area mask. However, its attainable throughput is considered to be about 10 sheets of 8-inch wafers at the most, which corresponds to about {fraction (1/10)} of the throughput by the current optical lithography. The X-ray proximity exposure method, on the other hand, has a problem that it is difficult to realize a mask having a sufficient accuracy.
Meanwhile, as a method for improving a resolution performance without changing an optical system in the optical lithography, a phase-shifting mask method is known. In this method, the resolution of the optical system is remarkably improved over the resolution when a conventional mask is used, by controlling (usually, inverting) the phase of light passed through a specific opening on a mask. There are various types of phase-shifting mask methods, among which an alternating phase-shifting mask method can provide the greatest resolution improving effect. The phase-shifting mask method is discussed, for example, in Handbook of Microlithography, Miromachining, and Microfabrication, Vol.1: Microlithography (SPIE Press, 1997, Bellingham, pp.71-82. The alternating phase-shifting mask method can be easily applied to an alternating pattern as its name implies, but it cannot be necessarily applied to a general pattern of any shape. For example, for Japanese-Character “⊃”-shaped pattern or a pattern having three opening patterns are arranged as mutually spaced by a shortest distance, it becomes difficult to obtain phase assignment. An example of a pattern having a difficult phase assignment is shown in FIG.
1
.
A method for performing multiple exposure over an identical resist film with use of a plurality of masks including a phase-shifting mask in order to enable transfer of a pattern having an arbitrary shape is filed by the inventors of the present application as Japanese Patent Nos. 2650962 and 2638561. This method is applied, in particular, to processing or the like of a logic LSI gate which requires formation of a highly-thin-line pattern by controlling its line width with a high accuracy. That is, a phase shifter (a region to be inverted in phase on a mask) is arranged so that the phases of openings on both sides of a gate are inverted, whereby a gate pattern can be remarkably improved in its resolution, line width accuracy, depth of focus, etc. However, an edge part of the shifter is transferred as an unnecessary pattern. In order to avoid it, the original design pattern is divided into two mask patterns for multiple exposure. Patterns on each of the above two masks can be automatically generated from the original design pattern through geometrical operations.
A method for generating two phase-shifting masks which can form any pattern based on multiple exposure using a phase retrieval method is suggested by Y. C. Pati, et al (in SPIE: Optical/Laser Microlithography VII, SPIE Vol. 2197 (1994), pp.314-327). This, in principle, proves that any pattern can be realized by the multiple exposure of the two phase-shifting masks.
Also suggested by B. J. Lin (in Japanese Patent Laid-Open Publication: JP-A-8-227140) is a method for dividing any pattern into horizontal and vertical patterns, using the both patterns respectively as a one-dimensional alternating phase-shifting mask, and performing multiple exposure over the both.
Also suggested by Ooi, et al (in Japanese Journal of Applied Physics, Vol. 33 (1994), pp.6774-6778) is a method, for the purpose of applying a phase mask method to a random pattern, for performing phase assignment over a figure at symbolic level and thereafter for performing compaction according to a phase relation between figures to thereby avoid phase conflicts. This method is intended to solve the phase conflicts by relaxing pattern dimensions for the phase conflict parts, which involves change of the design mask pattern itself. In addition, the method is not used to perform multiple exposure over two masks.
As mentioned above, however, we can say that, in the electron beam direct writing method, it is highly difficult to form such a random pattern as a wiring layer or active layer of a logic LSI with a practical throughput.
Meanwhile, it is difficult to apply the alternating phase-shifting mask method to a random pattern. In particular, the scale of a recent logic LSI exceeds such a level as manually designable, and thus the LSI is designed using an automatic place and route method. Accordingly, even formation of the phase-shifting mask phase-shifting mask is required to be carried out for a massive amount of pattern data generated automatically, which cannot be manually done by trial and error impractically. However, since the phase assignment method using the aforementioned phase retrieval method requires a very large amount of computation, it is practically difficult to process the massive amount of data in a practical time, and further a generated mask pattern becomes complex. Thus this method has a problem that the method necessarily pays no consideration to its actual mask manufacturing limit, etc.
The method for performing compaction after phase arrangement at symbolic level goes against the circuit miniaturization because the method relaxes the dimensions of the phase conflict parts.
In the method for dividing a pattern into v
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Nhu David
LandOfFree
Method for fabricating semiconductor device and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor device and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3143173