Library for use in designing a semiconductor device

Details Library for use in designing a semiconductor device Library for use in designing a semiconductor device

2001-06-04

2003-02-25

Mai, Son (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06526541

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a structure of a library used in circuit design of a semiconductor device.
Japanese Unexamined Patent Publication (A) No. H08-161389 discloses a method of calculating a delay time in signal transmission from an output terminal of a circuit cell to a branch node connected to the output terminal. Specifically, the method comprises the steps of obtaining a wire length from the output terminal of the circuit cell to each branch node connected to the output terminal, obtaining a total tree length of a tree forming an RC net (resistance-capacitance network) connected to the output terminal, calculating a ratio R
W
between the wire length and the total tree length, and calculating the delay time by the use of the ratio R
W
and the total tree length. In this case, the delay time is accurately calculated by calculating a variance V(R
W
) of R
W
or by clustering R
W
by the use of a standard deviation &sgr; of R
W
.
This invention relates to a library which is used in designing a logic circuit of a semiconductor device and which memorizes a delay value for each signal path of a circuit element of the logic circuit. As will later be described with reference to the drawing, the circuit element of the logic circuit is, for example, a unit logic gate having a plurality of inputs and a single output. The delay value for each signal path of the circuit element is different in object of delay calculation from the delay time on a wire from the output terminal of the circuit cell to the branch node connected to the output terminal in the above-mentioned publication. The above-mentioned publication does not disclose such library used in designing the logic circuit of the semiconductor device, such delay value for each signal path of the circuit element of the logic circuit, and any information related to the delay value.
A logic LSI or a logic circuit at a signal processing part of a memory LSI is produced by the steps illustrated in
FIG. 1
by the use of logic synthesis software. A technique of designing the logic circuit will presently be described.
A designer of the logic LSI describes a circuit function for realizing a circuit specification by the use of a hardware description language (HDL) such as Verilog-HDL. Referring to
FIG. 2
, the circuit function is described by Verilog-HDL. Referring to
FIG. 3
, the circuit having the circuit function described by the HDL is logically synthesized using circuit elements registered in the library.
The library comprises circuit elements including fundamental logic gates such as a NAND gate and macroscopic elements, such as a register and an adder, having fundamental functions. The logic synthesis software selects desired circuit elements from the library and synthesizes the circuit having the circuit function described by the HDL. The logic synthesis not only realizes the circuit function or logic described by the HDL but also optimizes a circuit velocity, a circuit area, and the like.
Referring to
FIG. 4
, a conventional library
10
′ used in the logic synthesis software includes a NAND gate and a part describing delay values of the NAND gate. The library
10
′ memorizes a minimum delay MIN as a best value, a typical delay TYP as a moderate value, and a maximum delay MAX as a worst value for each signal path of the NAND gate. Thus, the delay values in the velocity of each circuit element are determined depending upon a load condition. When the logic synthesis software is executed to select the desired circuit elements which satisfy the logic described by the HDL, the logic synthesis software can be set to select those circuit elements such that a minimum delay time is achieved.
Referring to
FIG. 5
, preparation of the library will be described. A test chip is produced and subjected to measurement of a device parameter such as a transistor threshold level (Vth). From the distribution of the device parameter, the maximum value (MAX), the minimum value ((MIN), and the typical value (TYP) of the device parameter are determined. Through circuit simulation based on these values, the maximum value (MAX), the minimum value (MIN), and the typical value (TYP) are determined for the delay values of the circuit element. These values thus determined are memorized in the library.
On the other hand, the circuit element has a predetermined area. Therefore, it is possible to execute the logic synthesis software with a setting such that a circuit area is minimized instead of a signal delay time of the circuit.
In the conventional circuit design described above, the variation in delay value of the circuit element is contained in the library as the minimum value and the maximum value. In most cases, the maximum value is set so that the probability of occurrence of a greater delay is about 0.1% or less. Such setting is generally called “3&sgr;”. This is because, in normal distribution of Gaussian distribution, a deviation from an average is equal to or greater than three times a standard deviation &sgr; at a probability of 0.1% or less.
However, the variation in delay value of the circuit element is assumed to be an independent event. Then, consecutive appearance of those circuit elements (for example, gates) having the maximum values is rare. If a large number of stages of circuit elements are contained upon the logic synthesis, evaluation is inclined to a greater delay than that actually obtained at a certain probability when the LSI is produced.
Referring to
FIG. 6
, a five-stage inverter circuit will be described by way of example. In the illustrated example, an average delay for each stage and 3&sgr; are assumed to be equal to 100 ps and 10 ps, respectively. Assuming that the variation in delay value of each inverter has a normal distribution and is completely independent of that of any other inverter, the total distribution as a sum of the normal distributions of such independent events has a variance which can be represented by a sum of variances of the distributions. By the use of 3&sgr; values registered in the library as the maximum values, the maximum value in delay value of the inverter circuit is estimated to be 550 ps. In the normal distribution, the variance is equal to a square of the standard deviation. Therefore, the variation of 50 ps is {square root over ( )}5 times excessive estimation. This problem is pointed out in “Design of CMOS ULSI” edited by Tetsuya lizuka, published by Baifu-kan, 1989, pp. 149-150.
In the conventional design technique, the independent variation in delay value of the signal path in each individual chip is considered by MIN, TYP, and MAX. However, no consideration is made about the independent variation in delay value of the signal path in each individual signal path in the LSI chip. Therefore, optimization of delay has been carried out by calculating a sum of the delay values defined in the library and by increasing the velocity of a slowest signal path. However, in the actual LSI, the variation in delay value of the signal path is independent in each individual path in the LSI chip. Therefore, the above-mentioned approach does not provide the optimization, as will presently be described. For convenience of description, each delay value is given by an integral multiple of 0.1 ns.
Referring to
FIGS. 7A and 7B
, it is assumed that a circuit having 1000 signal paths is synthesized by the logic synthesis software and that two circuit plans (a) and (b) are produced. Specifically, the plan (a) includes a single path having a delay of 5.1 ns and 999 paths having a delay of 4.9 ns while the plan (b) includes 1000 signal paths having a delay of 5.0 ns. In this event, the logic synthesis software selects the plan (a) as a best plan. However, if all of the signal paths have a variation of 0.2 ns as 3&sgr;, at least one path has a delay of 5.2 ns in most of the semiconductor devices in case of the circuit of the plan (a). On the other hand, the circuit of the plan (b) will be operated with a delay of 5.1 ns in the half or more of the semiconductor devices.
The circ

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