Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-01-10
2003-10-28
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S700000, C438S717000
Reexamination Certificate
active
06638871
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method for forming openings in low-k dielectric material layers.
2. Description of Related Art
In the semiconductor fabrication process, as the dimension of devices on a chip becomes smaller, the density of interconnect pitch becomes higher. Because widely used silicon oxide dielectric layers have high dielectric constants, it can easily result in high RC delay. Therefore, low dielectric constant (low-k) dielectric material is used instead as an inter-metal dielectric (IMD) in high speed ICs. To apply low k dielectric has the advantage such as reducing the interconnection parasitic capacitance, consequently reducing the RC delay, or mitigating the cross talk between metal lines, hence, the operation speed is improved. Hence, the low k dielectric material is a very popular IMD material used in high speed ICs.
The low k dielectric materials include inorganic materials, such as HSQ, FSG and CORAL, and organic materials, such as flare, SILK and parylene.
In the conventional via-first process for forming damascene opening, as shown in
FIG. 1
, a cap nitride layer
102
is formed over metal interconnects (not shown) within a provided substrate
100
. Afterwards, a first low-k dielectric layer
104
, a stop layer
106
, a second low-k dielectric layer
108
, a chemical mechanical polishing (CMP) stop layer
110
and a bottom anti-reflection coating (BARC) layer (not shown) are formed in sequence on the cap nitride layer. Then, a patterned first photoresist layer is formed on the BARC layer for defining vias. By using the first photoresist layer as a mask and the cap nitride layer is used as an etching stop layer, a first anisotropic etching process is performed through the layers to form a via opening.
After removing the first photoresist layer, a gap filling process is performed to fill the via with a polymer material layer to protect the cap nitride layer. After a patterned second photoresist layer is formed on the polymer material layer, a second anisotropic etching process is performed to define a trench, by using the stop layer as an etching stop layer.
FIG. 1
shows a prior-art damascene opening structure manufactured by the cited above process.
However, the polymer material layer covering the via opening provokes a fence profile
110
around top of the opening
120
, as shown in FIG.
1
. It is because the polymer material layer hinders the etching, resulting in incomplete removal of the second low-k dielectric layer
108
.
Furthermore, while the second photoresist layer is subsequently stripped by a photoresist removal process, such as a nitrogen/oxygen plasma ashing process or a nitrogen/hydrogen plasma process, the performed photoresist removal process usually damages the side walls
107
of the second dielectric layer
108
, leading to dielectric constant shift of the low-k dielectric layer. Moreover, the low-k dielectric material of the damaged sidewalls
107
tends to absorb moisture, resulting in degradation in the follow-up metallization process.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for forming openings in low-k dielectric material layer. The disadvantage of photoresist striping by plasma is improved, and no fence profile is provoked. Therefore, it is more advantageous for the fabrication for forming openings in low-k material layers, especially the low-k material layers containing metal wires or interconnects.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method for forming openings in low-k dielectric layers, A cap layer, a first dielectric layer, an etch stop layer, a second dielectric layer, a CMP stop layer, a metal hard mask layer, a hard mask layer and a BARC layer are formed in sequence on a provided substrate with metal wires. The first and second dielectric layers are low-k dielectric layers. Afterwards, a patterned first photoresist layer is formed on the BARC layer to define the BARC layer, the hard mask layer and the metal hard mask layer to form a first opening. Then, the first photoresist layer
220
is removed along with the BARC layer. Next, a BARC material layer is formed, acting as an anti-reflection layer and filling the first opening. Using a patterned second photoresist layer formed on the BARC material layer as a mask, a second opening is defined. After removing the second photoresist layer along with the BARC material layer, a damascene opening is formed by using the metal hard mask and the hard mask layers as a mask. Afterwards, the cap layer is removed and the dual damascene interconnect structure is completed.
By using the patterned hard mask layer and the patterned metal hard mask layer as a mask along with the gap-filling BARC material layer, the low-k dielectric layers are protected from plasma damage for stripping the photoresist. While the sidewalls of the second opening might be damaged during the photoresist stripping process, the damaged sidewalls will be removed during the following anisotropic etching process, thus avoiding degradation.
Moreover, no gap filling process is required for the via opening, thus avoiding the fence profiles.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6017817 (2000-01-01), Chung et al.
patent: 6197681 (2001-03-01), Liu et al.
patent: 6309955 (2001-10-01), Subramanian et al.
patent: 6350700 (2002-02-01), Schinella et al.
patent: 6372653 (2002-04-01), Lou et al.
patent: 6399478 (2002-06-01), Matsubara et al.
patent: 6455409 (2002-09-01), Subramanian et al.
patent: 2003/0044725 (2003-03-01), Hsue et al.
Chen Tong-Yu
Wang Chin-Jung
Chen Kin-Chan
United Microlectronics Corp.
Wu Charles C. H.
Wu & Cheung, LLP
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