Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-28
2003-10-21
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S370000, C257S371000, C257S372000, C257S376000, C257S377000, C257S206000, C257S390000, C257S401000
Reexamination Certificate
active
06635935
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a pattern configuration of a semiconductor device with a plurality of gate electrodes formed on a transistor forming region and arranged in one direction.
2. Description of the Background Art
Generally in designing a semiconductor integrated circuit within a semiconductor device, the entire semiconductor integrated circuit is not constructed at one time. Rather, a number of functional blocks, called standard cells, are combined under a prescribed rule to construct the semiconductor integrated circuit. Such method of combining a plurality of standard cells is called “cell-based design”.
The semiconductor integrated circuits of such cell-based design consisting of standard cells include a wide variety of circuits, from basic gate circuits with simple structures, such as inverter circuits, AND circuits and NAND circuits, more complex ones like flip-flop circuits, to relatively large sized block circuits like adders and so on, which are utilized as necessary.
As a rule of the cell-based design, unification in heights of standard cells, thicknesses of power supply lines, locations of wiring and input/output pins and others is attempted so as to place neighboring standard cells at a shortest possible distance from each other. As such standard cells, the one having a layout pattern as shown in
FIG. 13
, for example, has been utilized.
FIG. 13
schematically shows an underlying structure of a transistor portion in a conventional standard cell. A cell frame
21
delimited by a two-dotted, dashed line represents the standard cell region. This standard cell is provided with gate electrodes
1
,
2
,
3
and
4
arranged in a gate length direction, and active regions
5
,
6
and
7
formed by introducing impurity ions into a silicon substrate by ion implantation.
Gate electrodes
1
-
4
run across and extend beyond active regions
5
-
7
. Interconnection portions
15
,
16
,
17
and
18
in prescribed shapes are each provided at either end in a gate width direction of respective one of gate electrodes
1
-
4
.
Regions bounded by active regions
5
-
7
and gate electrodes
1
-
4
define source/drain regions
8
-
14
of transistors. For example, a transistor with gate electrode
1
has source/drain regions
8
,
9
. A transistor with gate electrode
2
has source/drain regions
9
,
10
. These two transistors share source/drain region
9
. Further, a transistor having gate electrode
3
is provided with source/drain regions
11
,
12
. A transistor having gate electrode
4
is provided with source/drain regions
13
,
14
.
Interconnection portions
15
-
18
are provided so as to electrically connect gate electrodes
1
-
4
to interconnections (not shown) which are to be placed in a layer overlying gate electrodes
1
-
4
. Normally, contact holes for connection between these interconnection portions and the interconnections in the upper layer are provided, so that gate electrodes
1
-
4
and the upper-layer interconnections are connected. Likewise, source/drain regions
8
-
14
are connected to the upper-layer interconnections by providing contact holes in those regions.
Thus, the gate electrode and the source/drain regions of each transistor are electrically connected to the interconnections in the upper layer, so that a logic circuit is constructed. Here, because of the configuration of the standard cell as described above, the size of the transistors can be set arbitrarily by changing the dimensions in the gate width direction of active regions
5
-
7
and gate electrodes
1
-
4
. As a result, it is readily possible to optimize the performance of the semiconductor integrated circuit.
On the contrary, in a so-called gate array structure, a basic size of transistor is predetermined, and the transistor size is only adjusted by an integer multiple thereof. This makes it difficult to optimize the circuit. Therefore, the cell-based design has an advantage that it can implement LSI (large-scale integration) exhibiting higher performance than in the gate array design.
In recent years, however, miniaturization of elements and interconnections has been drastically advanced and the pattern dimension has become smaller than the wavelength of light source of an exposure system. This causes variation in finished dimension of a pattern after exposure, which now is an innegligible problem. Specifically, in the case of exposure of a regular pattern, elements can be finished in approximately the same size. However, in the case of exposure of an irregular pattern for, e.g., the conventional gate electrodes as shown in
FIG. 13
, irregular interference of exposure light radiated from the exposure system will result in gate electrodes with their finished dimensions varying from one another.
Taking notice of gate electrode
2
in
FIG. 13
, for example, it is about twice the length of gate electrode
1
residing on its left side. In other words, gate electrode
1
extends along gate electrode
2
only half the way. In this case, finished dimension of gate electrode
2
in a portion adjacent to gate electrode
1
will differ from that in the remaining portion. Generally in a gate electrode, the gate length determines the performance of the transistor. If the gate length is longer than a designed value, load driving capability during an ON state of the transistor will decrease, thereby degrading the driving speed of the transistor. Conversely, if the gate length is shorter than the designed value, a leakage current during an OFF state of the transistor will increase, thereby increasing the power consumption.
As described above, in the case of cell-based design, if gate electrodes have an irregular pattern, their finished dimensions will vary from one another. This leads to performance degradation, such as a slower operating speed, increased power consumption and the like, of transistors within the semiconductor integrated circuit.
SUMMARY OF THE INVENTION
The present invention is directed to solve the above-described problems. An object of the present invention is to provide a semiconductor device having a pattern structure that can suppress performance degradation of transistors.
The semiconductor device according to the present invention includes: a transistor forming region having a plurality of source/drain regions formed on a semiconductor substrate and a plurality of gate electrodes arranged in a first direction, each having a gate width direction that matches a second direction orthogonal to the first direction; and a plurality of field effect transistors each formed of one of the plurality of gate electrodes and two of the plurality of source/drain regions. The plurality of field effect transistors include at least two kinds of such field effect transistors that are different in active region widths corresponding to lengths of the plurality of source/drain regions along the second direction. Each of the plurality of gate electrodes is made to have a gate width that is greater than the longest active region width.
As the gate width of each gate electrode is made greater than the longest active region width as described above, it is ensured that every couple of gate electrodes adjacent to each other have their sides facing with each other within the active region width. Thus, adverse effects of irregular interference of the exposure light can be suppressed, so that it becomes possible to equalize the finished dimension of each gate electrode.
As a preferred embodiment of the present invention, each of the plurality of gate electrodes is provided such that every distance between opposing sidewalls of two adjacent gate electrodes is approximately equal to each other. Still preferably, the plurality of gate electrodes have the same gate length.
With such a configuration, gate electrodes approximately in identical shapes are arranged regularly in the first direction. Thus, at the exposure step in the pattern formation of the gate electrodes, adjacent gate electrode pattern
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Soward Ida M.
Zarabian Amir
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