Method for forming a bit line for a semiconductor device

Details Method for forming a bit line for a semiconductor device Method for forming a bit line for a semiconductor device

2001-01-02

2003-11-18

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S587000, C438S622000

Reexamination Certificate

active

06649501

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a bit line for a semiconductor device and, in particular, to an improved method for forming a bit line for a semiconductor device that also improves the contact process for the semiconductor device.
2. Description of the Background Art If the minimum line width of a conventional DRAM cell is ‘F’, then the size of the unit cell will typically be approximately 10 F
2
.
Recent work has led to suggestions for a method of reducing the cell size to 8 F
2
. It appears that a cell size reduction from of 10 F to a cell size of 8 F
2
may be achieved without fundamentally changing the conventional processes and concepts.
However, a new cell layout and process concept are required in order to reduce the cell size to 6 F
2
. That is, using conventional methods, the cell size of 6 F
2
cannot be employed successfully for a highly integrated device.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for forming a bit line for a semiconductor device that can be used to fabricate a highly integrated semiconductor device having a cell size of 6 F
2
, by forming I-type active regions and a ladder-type bit line contacting the active regions in order to simplify subsequent contact processing.
In order to achieve the above-described object of the present invention, there is provided a method for forming a bit line for a semiconductor device, including the steps of: forming I-type active regions having a minimum line width on a semiconductor substrate, each active region being separated from adjacent active regions by the minimum line width distance; forming word lines having a minimum line width that are generally perpendicular to the I-type active regions, a pair of word lines crossing each I-type active region that leave three portions of the I-type active region exposed; forming a plug poly (polysilicon) on the active region between the word lines; forming an interlayer insulation film over the resultant structure; forming a bit line contact plug that overlaps the plug poly by a predetermined width; and forming a bit line having a minimum line width that overlaps the bit line contact plug by a predetermined width, the bit lines being oriented generally perpendicular to the word lines and generally parallel to the I-type active regions.


REFERENCES:
patent: 5170243 (1992-12-01), Dhong et al.
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5682055 (1997-10-01), Huang et al.
patent: 6008085 (1999-12-01), Sung et al.
patent: 6133599 (2000-10-01), Sung et al.

Affiliated with

Also associated with

Rating

Method for forming a bit line for a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming a bit line for a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a bit line for a semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3141707