Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-07-24
2003-12-16
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S685000, C257S686000, C257S787000
Reexamination Certificate
active
06664644
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor devices and to methods for manufacturing semiconductor devices. More particularly, the invention relates to a semiconductor device that is reduced in size to a CSP (Chip Size Package) level, and to a method for manufacturing such a semiconductor device.
2. Description of Related Art
With further size-reduction of mobile telephones and information terminals in recent years, there are demands that smaller and lighter parts be mounted on printed circuit boards, and also semiconductor devices, such as LSIs, are required to achieve a high mounting density with a chip stacked layered structure at a CSP level. The related art, for example, Japanese laid-open patent application HEI 11-204720, discloses a stacked level CSP type semiconductor device, such as the one shown in
FIG. 9
, in which diced first and second semiconductor chips
51
and
52
are bonded onto a dielectric substrate
55
having mounting external terminals
53
through dielectric adhesive layers
57
and
59
with device forming surfaces thereof face-up. Electrode pads on each of the semiconductor chips are connected to wiring sections
58
on the dielectric substrate
55
using wires
54
formed of Au, Al or the like, which are then sealed by a resin
56
.
Also, as disclosed in “Nikkei Micro Device,” February issue, on pages 38-67, or “Electronic Material,” September issue, on pages 21-85 in 1999, wafer level CSP type semiconductor devices that integrate a wafer processing process and a package assembly process are provided. They may be provided such that, by reducing the number of parts, such as interposers, and the number of processing steps, compared to conventional CSP types that are manufactured from single chips, the manufacturing cost is lowered, and the total cost of packages is lowered.
SUMMARY OF THE INVENTION
The above-described stacked level CSP type semiconductor devices that use wires also attempt to provide further miniaturization. However, because a bonding area needs to be secured for the second semiconductor chip on the surface of the first semiconductor chip, it is difficult to reduce the size in a direction parallel (lateral direction) to the chip surface.
Also, because a bonding area needs to be secured as described above, the design of a chip in an upper layer and the design of a chip in a lower layer need to be modified, for example, even when a memory capacity is desired to be simply increased.
Also, due to the capability of the wire bonding apparatus, control of wire pitches and spatial control over the wire configuration are difficult. Therefore, such semiconductor devices are not suitable for multiple-pin packages of large size LSIs.
On the other hand, the wafer level CSP type semiconductor devices have an advantage in that they can be miniaturized to a general chip size as viewed in plan. However, since it is difficult to form stacked layers, the above described related art semiconductor devices have certain limitations in achieving a higher mounting density, even though such a higher mounting density is desirable.
The present invention addresses the circumferences described above, and provides highly reliable semiconductor devices that can achieve further miniaturization and higher mounting density. The present invention also provides methods for manufacturing such semiconductor devices.
To address the problems described above, a semiconductor device in accordance with the present invention provides a first semiconductor chip disposed facedown on a surface of a tape substrate, and a second semiconductor chip disposed face-up on a rear surface of the first semiconductor chip. The semiconductor device also includes:
a wiring pattern formed on the surface of the tape substrate;
a mounting external terminal formed on a rear surface of the tape substrate;
an external terminal of the first semiconductor chip connected to the wiring pattern;
a bonding pad formed on a surface of the second semiconductor chip;
a bonding wire that connects the bonding pad and the wiring pattern; and
a resin that seals the surface of the tape substrate, the bonding wire, and the first and second semiconductor chips.
With the semiconductor device described above, the first semiconductor chip is connected to the wiring pattern on the tape substrate with the external terminal, and the second semiconductor chip is connected to the wiring pattern on the tape substrate with the bonding wire. In this manner, the number of chips that use bonding wires is reduced, such that the degree of freedom and flexibility in designing the second semiconductor chip are enhanced. Also, a bonding area does not need to be secured on the surface of the first semiconductor chip, the chip size in the direction parallel to the chip surface (lateral direction) can be reduced, whereby further miniaturization and greater density of semiconductor devices can be realized. Also, control of wire pitches of bonding wires and spatial control of wire configurations become easier. Lowering of the reliability that may be caused by bonding wires can be reduced or avoided, and the reliability of semiconductor devices can be enhanced.
A semiconductor device in accordance with another aspect of the present invention includes a first semiconductor chip disposed face-down on a surface of a tape substrate, a second semiconductor chip disposed face-up on a rear surface of the first semiconductor chip, and a third semiconductor chip disposed face-up on a surface of the second semiconductor chip. The semiconductor device also includes:
a wiring pattern formed on the surface of the tape substrate;
a mounting external terminal formed on a rear surface of the tape substrate;
an external terminal of the first semiconductor chip connected to the wiring pattern;
a first bonding pad formed on the surface of the second semiconductor chip;
a second bonding pad formed on a surface of the third semiconductor chip;
bonding wires that connect the wiring pattern to the first bonding pad and the second bonding pad, respectively; and
a resin that seals the surface of the tape substrate, the bonding wire, and the first through third semiconductor chips.
Also, the semiconductor device in accordance with the present invention may further include a metal post formed between the external terminal and the surface of the first semiconductor chip, and a resin that seals circumferential areas of the metal post and the surface of the first semiconductor chip.
Also, in the semiconductor device in accordance with the present invention, the metal post may preferably be formed from a plated film or a metal ball.
Also, the semiconductor device in accordance with the present invention may further include a resin that seals circumferential areas of the external terminal and the surface of the first semiconductor chip. A surface of the external terminal may be exposed through the resin.
A semiconductor device in accordance with another aspect of the present invention includes a first semiconductor chip disposed face-down on a surface of a tape substrate, a second semiconductor chip disposed face-down on a rear surface of the first semiconductor chip, and a third semiconductor chip disposed face-up on a rear surface of the second semiconductor chip. The semiconductor device also includes:
a wiring pattern formed on the surface of the tape substrate;
a mounting external terminal formed on a rear surface of the tape substrate;
an external terminal of the first semiconductor chip connected to the wiring pattern;
an external terminal of the second semiconductor chip connected to the wiring pattern;
a bonding pad formed on a surface of the third semiconductor chip;
a bonding wire that connects the bonding pad and the wiring pattern; and
a resin that seals the surface of the tape substrate, the bonding wire, and the first through third semiconductor chips.
A semiconductor device in accordance with another aspect of the present invention includes a first semiconductor chip disposed face-down on a surface of
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