Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-02-12
2003-06-10
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S111000, C711S112000, C711S115000, C711S172000
Reexamination Certificate
active
06578125
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a memory access circuit or memory access control circuit and, more particularly, to a memory access circuit or memory access control circuit for enabling access through a controller provided on an unloadable recording medium to a memory in the same recording medium.
2. Description of the Prior Art
The recording mediums, to be removably received in electronic appliances, include those such as compact flashes accessible to the semiconductor memory through the controller provided on the medium. Herein, there is a tendency that the access rate of the controller increases with the increase in memory capacity. That is, as the semiconductor memory capacity is increased by the advancement of technology, the access rate of the controller also increases owing to the technological advancement. In the prior art, however, the access control signal for the controller has an active period having been set comparatively long in order to enable positive access even where a small-capacity recording medium is inserted. Thus, it has been impossible for the controller to exhibit its capacity to a full extent.
SUMMARY OF THE INVENTION
Therefore, it is a primary object of the present invention to provide a memory access circuit or memory access control circuit by which a controller provided on a recording medium can exhibit its capacity to a full extent.
A memory access circuit according to the present invention comprises: a holder for holding a removable recording medium having a memory and a controller to access the memory in response to an access control signal; an outputter for outputting the access control signal to the controller; a detector for detecting a capacity value of the memory; first setter for setting an active period for the access control signal to a first period when the capacity value is below a predetermined threshold; and a second setter for setting an active period for the access control signal to a second period shorter than the first period when the capacity value is greater than the predetermined threshold.
The recording medium to be held by the holder is a removable recording medium having a controller for access to a memory in response to an access control signal and a memory. The capacity value of the memory is detected by the detector. A detected capacity value is compared with a predetermined threshold by the comparator. When the capacity value is below the predetermined threshold, the active period for the access control signal to be outputted to the controller by the outputter is set to a first period by the first setter. Contrary to this, when the capacity value is greater than the predetermined threshold, the active period for the access control signal is set to a second period shorter than the first period by the second setter.
That is, it is considered that the controller can realize access at higher speed as the capacity of the memory increases. Thus, when the capacity value is greater than the predetermined threshold, the active period for the access control signal is made short. Consequently, it is possible for the controller provided on the recording medium to exhibit to a maximum extent.
Preferably, the memory stores capacity value data, and the detector detecting the capacity value by reading the capacity value data from the memory according to the access control signal.
Also, the access control signal preferably contains an enable signal, the enable signal having an active period set to either one of the first period or the second period.
A memory access control circuit, comprises: a holder for removably holding a recording medium having a memory storing a data signal and a controller to read the data signal from the memory in response to a read control signal; an outputter for outputting to the controller a plurality of read control signals different in active period from one another; determiner for determining whether each of the plurality of data signals read in response to the plurality of read control signals is proper in data value or not; and an enabler for enabling a shortest active period among the active periods corresponding to determination results that the data value is proper.
The recording medium to be removably held by the holder has a memory and a controller to read a data signal from the memory in response to a read control signal. The outputter outputs to the controller a plurality of read control signals different in active period from one another. When a plurality of data signals are read from the memory in response to the read control signals, the determiner determines whether each of read-out data signals is proper in data value or not. The first enabler enables a shortest active period among the active periods corresponding to determination results that the data value is proper.
In this manner, determination is made as to properness in data value on the data signals read out by the read control signals different in active period from one another. Activation is made for the shortest active period among the active periods corresponding to the determination results as proper. Accordingly, the controller is allowed to exhibit its performance to a maximum extent.
In one aspect of this invention, the memory stores a common data signal that is common to respective ones of the recording medium, each of the plurality of read control signals including storage-destination address information for the common data signal, and the determiner determining whether the common data signal read from the memory exhibits a predetermined value or not.
In another aspect of this invention, a capacity value of the memory is detected by detector, and the outputter is enabled by the enabler when the capacity value exceeds a predetermined threshold.
Preferably, the memory stores a capacity value data signal representative of the capacity value, and the detector detecting the capacity value by reading the capacity value data signal.
The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5291468 (1994-03-01), Carmon et al.
Armstrong Westerman & Hattori, LLP
Bragdon Reginald G.
Inoa Midys
Sanyo Electric Co,. Ltd.
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