Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-12-03
2003-10-21
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S723000, C438S724000
Reexamination Certificate
active
06635576
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method a creating borderless contact holes.
(2) Description of the Prior Art
The continued striving in the semiconductor industry for improving the performance of semiconductor devices has led to a continued trend in the reduction of device parameters and a reduction in the lengths of paths that are required to interconnect semiconductor devices. Device densities have as a consequence increased dramatically as have the number of semiconductor chips that can be created using one substrate, thus controlling and reducing the device costs. All of these trends have been made possible by gradual but significant advances in the available technologies and tools while continued advances in the materials that can be applied for the implementation of device characteristics have been key to the advancements that have been achieved in the semiconductor industry. Most significant in the new methods that have been applied in the creation of semiconductor devices are advances in methods and tools of photolithography (in addition to the application of more sensitive photoresist materials) and the application of new, dry etching procedures, most notably the application of Reactive Ion Etching (RIE).
As previously stated, higher device performance and improved functional capacity in integrated circuits require reduction of device Critical Dimensions (CD) and increased packaging density of the devices. Such requirements however require tight tolerance of pattern definition. To meet the required tolerance of critical dimensions presents a challenge to conventional photolithographic techniques for patterning contacts for very small sub-micron or sub-half-micron or even sub-quarter-micron modern silicon devices. Silicides are often used to reduce contact resistance in forming contact points to gate electrodes of a MOSFET device. The method of self-aligned silicide (salicide) formation helps to solve the problem of critical dimension tolerance. Using this method, the contact points that are formed for the source and the drain of the gate electrode self-align with the polysilicon gate. Salicides are therefore almost universally applied in today's high-density MOSFET devices.
There are however problems associated with methods of salicide formation such as the consumption of silicon underlying the metal, resulting in the consumption of silicon (of the substrate) over the surfaces of the source and drain regions, resulting in creating source/drain regions that are extremely thin. A further problem is that the salicidation reaction can consume substrate silicon unevenly, leading to ragged source/drain junctions. Another problem that is directly related to the reduction in device CD's is that electrical shorts can occur between the contact points that are formed over the gate structure and the source/drain regions. It is therefore, with ever smaller device dimensions, becoming increasingly more difficult to create gate and source/drain points of electrical contact while maintaining the required low sheet resistance and low junction leakage current for the contact points. Of special concern in this respect is the potential for misalignment of the photolithographic exposure for the creation of points of contact to the source/drain regions of a CMOS device. This can result in a contact opening that is too far removed from the CMOS device, partially exposing the non-salicided surface of the silicon substrate, or in a contact opening that is too close to the CMOS device, partially exposing the gate electrode spacers and creating the risk of etching (the contact opening) to the silicon substrate or causing a short with the (polysilicon of the) gate electrode. The invention addresses these concerns by providing a method of creating borderless contacts using a graded-stair dielectric layer as an etch stop layer.
U.S. Pat. No. 6,074,908 (Huang) shows a borderless contact method.
U.S. Pat. No. 6,072,237 (Jang et al.) and U.S. Pat. No. 6,046,103 (Thei et al.) show borderless contact processes with stop layers.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method of creating borderless contact holes using multiple layers of overlying dielectric that function as an etch stop layer for the creation of a borderless contact hole.
Another objective of the invention is to create a borderless contact hole of improved contact resistance and of improved leakage current performance characteristics.
Yet another objective of the invention is to provide a contact hole for contacting source/drain regions of a CMOS device whereby the proximity of the contact hole to adjacent surface regions of Field Isolation oxide is reduced.
A still further objective of the invention is to provide a method of creating a borderless contact hole whereby control of Critical Dimensions of the contact hole can be relaxed.
A still further objective of the invention is to create a borderless contact hole through a layer of dielectric overlying at least one gate electrode whereby the control of the thickness of the layer of dielectric can be relaxed.
A still further objective of the invention is to provide a method of creating a borderless contact hole whereby the alignment between the photolithographic exposure for the contact hole and the subsequently performed etch of the contact hole can be relaxed.
In accordance with the objectives of the invention a new method is provided for the creation of borderless contact holes that are created to the source/drain regions of CMOS devices. A gate electrode is created over the surface of a substrate, three consecutive, relatively thin layers of dielectric are deposited over the exposed surfaces of the gate electrode and the surface of the substrate surrounding the gate electrode. From these three layers an etch stop layer is created for the etching of the contact hole through the main, relatively thick layer of dielectric that is deposited overlying the gate electrode. By selecting known and mutually dependent etch rates for the three relatively thin layers of dielectric, the etch of these three layers can be controlled, thereby controlling the depth and the surface area that is being etched in an interdependent manner through the three layers of dielectric. An opening can therefore be etched through the upper two layers of dielectric, leaving the lower layer of dielectric in place overlying the surface of the source/drain regions. The main, relatively thick layer of dielectric overlying the gate electrode and through which contact holes are to be created is then deposited, contact holes are etched through this main layer of dielectric aligned with the holes that have been etched through the upper two layers of the etch stop layer. The lower layer of the three relatively thin layers of dielectric serves as an etch stop layer for the etch of the contact hole through the main layer of dielectric, the lower layer is partially removed after the contact hole has been etched through the main layer of dielectric.
REFERENCES:
patent: 5792703 (1998-08-01), Bronner et al.
patent: 6020255 (2000-02-01), Tsai et al.
patent: 6046103 (2000-04-01), Thei et al.
patent: 6072237 (2000-06-01), Jang et al.
patent: 6074908 (2000-06-01), Huang
patent: 6225211 (2001-05-01), Tsui
patent: 6323118 (2001-11-01), Shih et al.
patent: 6339027 (2002-01-01), Chok
Lin Kwang-Ming
Liu Meng-Chang
Wu Lin-June
Ackerman Stephen B.
Chen Kin-Chan
Saile George O.
Taiwan Semiconductor Manufacturing Company
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