Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-05-12
2003-02-25
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S381000, C257S383000, C257S385000, C257S390000, C257S903000
Reexamination Certificate
active
06525382
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory device in which memory cells have a CMOS (Complementary Metal Oxide Semiconductor) configuration such as SRAM (Static Random Access Memory) cells having six transistors and the like. Specifically, this invention relates to a semiconductor memory device and a method of manufacturing the same, which are suitable for the split word line type SRAM in which word lines are placed in each word transistor separately.
2. Description of the Related Art
A SRAM cell generally has a latch and two transistors (word transistors). On-off operations of the transistors are controlled based on the voltage applied to a word line and thereby connection between each of two memory nodes of the latch and a bit line is made or broken. The latch is composed of two inverters. An input terminal and output terminal of each of the inverters cross over each other by two sets of node wiring (wirings between memory nodes and gate electrodes) and connect to a bit line.
The SRAM cells can be broadly divided into two types, namely a MOS transistor load type and a high resistance load type, based on a difference in a load element of the latch. The SRAM cells of the MOS transistor load type, configured with six transistors, fall into two types: a P-channel MOS transistor (hereinafter referred to a pMOS) load type and a TFT (Thin Film Transistor) load type, according to the type of its load transistor.
In recent years, a so-called split word line type SRAM cell in which the word lines are separately placed in each word transistor has been proposed in a “A LOW COST MICROPROCESSOR COMPATIBLE, 18.4 &mgr;m
2
, 6-T BULK CELL TECHNOLOGY FOR HIGH SPEED SRAMS” (VLSI Symposium report PP65-66, 1993). In the split word line type SRAM cells described in this report, n-type drive transistors are connected in series and word transistors are placed so as to be orthogonal to the n-type drive transistors at both ends of the cell.
In the case of forming this type of SRAM cell, a pattern design determined by the limit of an exposure system is employed in order to realize the minutest cell size. That is, in a conventional type of SRAM cell, two sets of node wiring crossing over each other are simultaneously patterned so that the space between the two sets of node wiring is defined by the limit of exposure of the exposure system, thereby making it impossible to further reduce the cell size.
As one of the techniques to solve the foregoing problems, it is proposed that node wiring of the SRAM cell is patterned separately in two steps (M. Ishida et al, IEDN Tech. Dig., P201, 1998). This technique is used, for example, when node wiring R
161
b
and S
161
a
shown in
FIG. 1
are separately formed in different steps. As compared with the conventional technique such that all the node wiring is formed at the same time using a single photo mask, this technique realizes a wiring pattern on a photo mask which has smaller space by the amount that space between resist patterns of the wiring pattern is reduced. As a result, the space between the two sets of node wiring can be made small irrespective of the limit of exposure of the exposure system.
In this type of SRAM cell, it is desirable to provide landing pad layers on contact holes to be connected to a bit line or the like. The landing pad layers are provided so as not to increase a resistance between plugs in case there is a slightly matching shift at the time of forming the contacts for burying upper plugs. To simplify the process, the landing pad layers are preferably formed in the same layer, i.e., in the same step as the node wiring.
However, in the conventional resist patterning described above, each distance between the node wiring and the contacts was small, and thus there was no space so for the landing pad layers to be formed in the same layer as the node wiring layer. Moreover, as illustrated in the
FIG. 1
, in the conventional pattern, all memory cells are formed consecutively in the same direction. As a result, even if the node wiring is patterned separately in two steps, the landing pad layers are disposed close to both of the two sets of node wiring, thereby making it impossible to form the node wiring and the landing pad layers in the same layers, i.e., in the same step.
The invention has been designed to overcome the foregoing problems. The first object of the invention is to provide a semiconductor memory device which includes landing pad layers in correspondence to contacts connecting a grounded line, power supply voltage line and bit line in the same layer as node wiring, the contacts being capable of functioning even though there exists a slight matching shift when forming the contacts. Consequently, it is possible to simplify the manufacturing process and make high integration feasible.
The second object of the invention is to provide a method of manufacturing a semiconductor memory device which may easily form landing pad layers for contacts connecting to a grounded line, supply line and bit line in the same layer as node wiring, and therefore simplify the manufacturing process and realize high integration as well.
SUMMARY OF THE INVENTION
In a semiconductor memory device according to the invention, two inverters included in each cell, consist of a first conductive drive transistor and a second conductive load transistor to which a common gate is connected, the first conductive drive transistor and the second conductive load transistor being connected in series between a first power supply voltage line to supply a first power voltage and a second power supply voltage line to supply a second power voltage. In the two inverters input terminals and output terminals are connected crossing over each other by two sets of node wiring. Furthermore, in this semiconductor memory device, each pattern of the two sets of node wiring has the same shape in each cell and is disposed in a different direction from each other between neighboring cells.
A method of manufacturing a semiconductor memory device comprises: a step in which a conductive film is first formed to become first node wiring, second node wiring, first landing pad layers and second landing pad layers after which a film having a slower etching rate than the conductive film is formed on the surface of the conductive film: a step of forming etching mask layers by processing the film with the slower etching rate using a pattern of the first node wiring and a pattern of the first landing pad layer; and a step of forming the first node wiring and the second node wiring together with the first landing pad layers and the second landing pad layers, the first node wiring and the second node wiring being formed by processing the conductive film using a pattern of the second node wiring and a pattern of the second landing pad layer while protecting the conductive film disposed immediately below the etching mask layer with the etching mask layer.
In the semiconductor memory device according to the invention, each pattern of the two sets of node wiring is disposed in a different direction between neighboring cells in up-down and right-left directions. As a result, the two sets of node wiring are formed to have the same pattern with a roughly C shape, and are arranged to engage with each other, thereby making it possible to have a configuration in which the landing pad layers are formed of the same conductive material as the node wiring in the same layer as the two sets of wiring.
In the method of manufacturing the semiconductor memory device, the first and second node wiring are formed separately in two different steps. Therefore, space between the node wiring can be made small by the amount that space between resist patterns of node wiring is reduced, and the first landing pad layer and the second landing pad layer are made of the same conductive film as the first and second node wiring. Specifically, the first landing pad layer and the second landing pad layer are formed with a wide margin due to the following arrangement. A patter
Kananen, Esq. Ronald P.
Nadav Ori
Rader & Fishman & Grauer, PLLC
Sony Corporation
Thomas Tom
LandOfFree
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